Command processing method and its applicable super-scale pipeline microprocessor

Abstract

A super-scale pipeline microprocessor and command processing method. The super-scale pipeline microprocessor has a register aggregation, a high speed cache, a performing unit and a load application unit coupled to the high speed cache, that are defined by the command set framework of the super-scale pipeline microprocessor. The load application unit is different from other performing units of the super-scale pipeline microprocessor, and the load application unit includes an arithmetic logic unit. The load application unit receiving a first command, the first command designates the first storage address of the first origin operand, operation performed on the first origin operand and generating result, and a first destination register in the register aggregation to store the result. The load application unit reads the first origin operand from the high speed cache. The arithmetic logic unit performs operation on the first origin operand to generate result, rather than forwarding the first origin operand to anyone of the other performing units to perform operation on the first origin operand to generate result. The load application unit further outputs the result for subsequent fallback to the first destination register.

Description

Technical field [0001] The present invention mainly relates to the technical field of microprocessors, and particularly relates to a microarchitecture of a microprocessor. Background technique [0002] A typical example of a reduced instruction set architecture processor is that this processor uses a load / store architecture, that is, this processor includes a load instruction to load an operand from the memory to the processing This processor also includes a storage instruction for storing an operand in a register of the processor into the memory. In a general example, the above load and store instructions are the only instructions that will access the memory, while other instructions that perform arithmetic / logical operations receive their operands from the registers and write the results to the registers, meaning that they are not loaded Or stored instructions are not allowed to specify the operands in the memory, which allows most non-load or stored instructions to be execute...

AI Technical Summary

Problems solved by technology

[0004] The advantage of using different load / store units and ALUs is that the architecture is simple and fast. However, the disadvantage is that it takes a lot of time to transfer the results between the various units through the registers. Part of this problem can be solved by transferring The transfer bus is used to transfer a result from one execution unit to another directly without going through registers, but this still has the problem of time consumption, that is, the delay that occurs during the transfer ( delay) situation

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