Internal memory and storage device

Abstract

The invention relates to an internal memory and a storage device. The internal memory comprises a plurality of word lines, a first bit line, a second bit line, a third bit line and a plurality of storage units, wherein the word lines are in parallel arrangement in turn; the first, second and third bit lines are perpendicular to the word lines and in parallel arrangement in turn; and each storage unit corresponds to a word line and a bit line. The word line corresponding to each storage unit corresponding to the first bit line is different from the word line corresponding to each storage unit corresponding to the second bit line. As the storage units are arranged in the internal memory in a staggered form, the noise interference (caused by coupling capacitance) of the adjacent bit line canbe avoided. In addition, the pullup load is not needed to add. Therefore, the cost of components can be reduced and the power loss of the internal memory can be not increased.

Description

technical field [0001] The present invention relates to a memory and storage device, in particular to an arrangement structure of storage units of a storage device. Background technique [0002] figure 1 It is a schematic diagram of the arrangement of known memory cells. As shown in the figure, when the word line WL is enabled, the memory cell C 0 ~C 3 The transistors within are turned on, therefore, the bit line BL 0 ~BL 3 Then the corresponding level can be output. exist figure 1 , when the storage unit C 0 ~C 3 All transistors within are turned on, except the bit line BL 1 is the output high level, other bit lines (such as BL 0 、BL 2 、BL 3 ) are output low level. [0003] However, the bit line BL 1 with adjacent bit lines (such as BL 0 and BL 2 ) There is a coupling capacitance between them. Therefore, the bit line BL 1 Due to the influence of the coupling capacitor, an incorrect level (such as a low level) may be output. To solve this problem, a known ...

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Problems solved by technology

Therefore, the bit line BL 1 May be due to the influence of the coupling capacitor, thus outputting an incorrect level (such as a low level)

In order to solve this problem, a known solution is to couple a pull-up load to the bit line, but this will increase the cost

In addition, the additional pull-up load will form a redundant current path (current path), thus increasing power loss

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