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Wafer holding mechanism, wafer holding system and wafer matched with wafer carrier

A chip carrier and chip technology, applied in the direction of electric solid-state devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problem of difficult removal of the chip 105, to save manufacturing costs, reduce costs and consumption Effect

Active Publication Date: 2010-09-08
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if the adhesion of the adhesive 115 is too good, it will be difficult to remove the wafer 105 from the wafer carrier 110 once the process is completed.
Furthermore, once the wafer 105 is removed, the residue left by the adhesive 115 will require additional cleaning steps
And, the step of removing the wafer 105 should be relatively simple and not easy to damage the wafer 105, but so far, the existing adhesive tapes or adhesive materials cannot meet the above requirements

Method used

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  • Wafer holding mechanism, wafer holding system and wafer matched with wafer carrier
  • Wafer holding mechanism, wafer holding system and wafer matched with wafer carrier
  • Wafer holding mechanism, wafer holding system and wafer matched with wafer carrier

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Embodiment Construction

[0044] The embodiment of the present invention will describe the specific background technology, that is, the integrated circuit manufactured by the die-on-top technology. However, the present invention can also be applied to integrated circuits manufactured using other process technologies as long as the level of the wafers used to manufacture the integrated circuits needs to be maintained during the process.

[0045] Figure 2a is an isometric view of a wafer holding system 200 for holding a wafer 205 for fabrication in accordance with an embodiment of the present invention. According to an embodiment of the present invention, when the integrated circuits are fabricated on the wafer 205, the wafer 205 can be placed on a wafer carrier 210, so that the handling of the wafer 205 can be simple and safe.

[0046]In order to make the alignment of the wafer 205 on the wafer carrier 210 more precise, the wafer carrier 210 may have a plurality of alignment posts (eg, alignment posts...

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PUM

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Abstract

A system and method for integrated circuit fabrication is provided. A wafer holding system includes a wafer carrier that holds the wafer at a specified alignment, and a top ring disposed on a top surface of the wafer and of the wafer carrier. The top ring holds the wafer and the wafer carrier together as a single unit. The wafer carrier includes an alignment mechanism to hold the wafer in the specified alignment.

Description

technical field [0001] The present invention relates to an integrated circuit, and in particular to an integrated circuit manufacturing system and method. Background technique [0002] The development of integrated circuits has affected almost every aspect of modern life. The application of integrated circuits has made such devices as computers, imaging equipment, audio equipment, automobiles, electrical appliances, and similar equipment more reliable and at the same time satisfying lower prices. , making integrated circuits attractive. [0003] The manufacture of integrated circuits includes integrated circuit structures on a substrate that is only a portion of a wafer that is subsequently diced into individual dies. With the development of process technology, the size of the wafer is gradually increasing and the thickness is gradually becoming thinner. Due to the complicated process technology for manufacturing the required wafer size and thickness today, it is necessary ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/687H01L23/544
CPCH01L21/68721H01L21/6836H01L2223/54426H01L2221/68327H01L21/6835H01L23/544H01L2924/0002H01L2924/00
Inventor 李柏毅王宗鼎
Owner TAIWAN SEMICON MFG CO LTD
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