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Processor Cache write-in invalidation processing method based on memory access history learning

A processing method and processor technology, applied in memory systems, electrical digital data processing, instruments, etc., can solve problems such as difficult and efficient support of memory access characteristics in write allocation strategies, and achieve the effect of improving performance and reducing bandwidth waste

Active Publication Date: 2010-06-23
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Different applications have different memory access characteristics, and it is difficult for a fixed write allocation strategy to efficiently support these different memory access characteristics at the same time

Method used

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  • Processor Cache write-in invalidation processing method based on memory access history learning
  • Processor Cache write-in invalidation processing method based on memory access history learning
  • Processor Cache write-in invalidation processing method based on memory access history learning

Examples

Experimental program
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Effect test

example 1

[0086] Example 1. Assume that the memory access invalidation queue has the following three items, among which item 0 and item 1 are valid, and their addresses are 0x0401000 and 0x001f00c0 respectively. Item 0 of the two items is delayed write allocation, and item 1 is immediate write allocation. . Among them, 16 bytes of data from 0x0401000 to 0x0401000f have been stored in item 0. Then the addresses of the four words and operations entering the memory access unit are 0x0401001c, 0x04010010, 0x04010014, 0x04010018 respectively. These four operations will miss the cache and enter the memory access invalidation queue. After address comparison, these four operations all fall within the range of item 0 of the queue, so these four operations also inherit the delayed write allocation of item 0. The memory read request is delayed until the fourth write operation also enters the memory access invalidation queue. At this point, item 0 has collected the entire cache block, so there is ...

example 2

[0087] Example 2. Assume that there are 3 items in the memory access invalidation queue, of which item 0 and item 2 are valid, and their addresses are 0x04000000 and 0x007f0040 respectively. The second item in the two items is delayed write allocation, the delay field is set to 1, and item 0 For immediate write allocation, that is, the delay field is set to 0. At this time, a byte write operation with an address of 0x007f00c8 enters the memory access unit. After searching, it misses in the Cache, so it needs to enter the memory access invalidation queue. By comparing the addresses with the existing two items in the memory access queue, the new write failure does not fall into any of the items, so a new item is assigned to it in the memory access invalidation queue. Therefore, the first item is valid, the address field is set to 0x007f00c0, the 64 to 71 bits of the data field store the value to be written in the write operation, and the eighth bit of the mask byte mask field is...

example 3

[0088] Example 3. Assume that there are 3 items in the memory access invalidation queue, of which item 0 and item 2 are valid, and their addresses are 0x04000000 and 0x007f0040 respectively. Item 2 of the two items is delayed write allocation, and item 0 is immediate write allocation. Only one word of data at address 0x0400000c is stored in item 2. At this time, a byte read operation whose address is 0x04000004 enters the memory access unit, and it misses in the Cache after searching, so it needs to enter the memory access invalidation queue. By comparing the address with the existing two items in the memory access queue, it is judged that it falls in item 0, but after further searching, it is found that the required data is not currently in the data field, so the delay field of item 0 is set to 0 , immediately initiate a memory read access.

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Abstract

A processor Cache write-in invalidation processing method based on memory access history learning includes the following procedures: (1) Cache invalidation preprocessing procedure; (2) Cache write-allocation strategy setting procedure includes that: the immediate write-allocation or delay write-allocation strategy of each group is set; (3) the group belonging to the immediate write-allocation immediately accesses the Cache block corresponding to the memory and reads the missing data of the group back, and integrates the missing data with the write-in data to form complete Cache block data, and writes the complete Cache block data into the corresponding Cache block; the group belonging to the delay write-allocation collects the write-in data of Cache write-in invalidation operation allocated in the group, and writes the write-in data directly into the corresponding Cache block when the write-in data of a certain group is fully collected in the whole Cache block. The invention can reduce great unnecessary operations of reading Cache block from the memory during the processing process of the Cache write-in invalidation, accordingly reduces the bandwidth waste of the process and further improves the performance of the application program.

Description

technical field [0001] The invention belongs to the technical field of computer processors, and more specifically relates to a processor cache (Cache) write invalidation processing method. Background technique [0002] In the field of computer architecture design, many memory access optimization technologies have been proposed to bridge the performance gap between processors and memory, including non-blocking Cache, prefetching, and prediction related to memory access instructions. These technologies focus more on how to reduce or tolerate memory access delays. time, but usually at the expense of memory access bandwidth. In a multi-threaded, on-chip multi-core processor structure, the effective bandwidth provided by the processor becomes an important factor affecting the acceleration of the multi-threaded multi-core processor. Therefore, it is not enough to optimize the memory access performance of the processor only from the perspective of delay, and the optimization of ba...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G06F9/34
Inventor 汪文祥李祖松郝守青徐翠萍
Owner LOONGSON TECH CORP
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