Mistuning self-correctional high-speed data comparison latch

Abstract

The invention discloses a mistuning self-correctional high-speed data comparison latch which comprises an input geminate transistor P, an input geminate transistor N, a comparison latch module, an input control module, an output control module and a mistuning logic control module, wherein the input control module generates two signals to respectively control the input geminate transistor P and theinput geminate transistor N; then the input geminate transistor P and the input geminate transistor N are respectively output and are connected with the comparison latch module; latch output of the comparison latch module is connected with the output control module and the mistuning logic control module at the same time; the output control module are output to a sampling device; and the mistuninglogic control module generates two adjusting signals for respectively adjusting the number of geminate transistors of the input geminate transistor P and the input geminate transistor N according toa reset signal RESET and the latch output signal output by the comparison latch module, and adjusts the number of the geminate transistors of the two input geminate transistors to realize mistuning self-correction. The invention automatically corrects the number of differential input geminate transistors through a feedback mechanism to correct operating points and threshold voltages of the differential input geminate transistors and eliminate process deviation, and the differential input geminate transistors of the high-speed data comparison latch in a receiver are exactly matched.

Description

technical field [0001] The invention relates to a high-speed data comparison latch, in particular to an offset self-correcting high-speed data comparison latch. technical background [0002] High-speed analog-to-digital conversion circuits are an important part of modern high-speed communication and signal processing circuits, and the design of high-speed data comparison latches is a key link in the design of high-speed analog-to-digital converters. In any high-speed and high-resolution analog-to-digital converter, the high-speed data comparison latch determines the highest resolution and the fastest conversion speed of the digital-to-analog converter to a large extent. However, in the high-speed data comparison latch, the mismatch of the differential input pair tube determines the comparison accuracy of the high-speed data comparison latch to a certain extent, and at the same time reduces the latch timing margin of the high-speed data comparison latch , thus affecting the ...

AI Technical Summary

Problems solved by technology

[0004] When self-correction technology is not used, a good CMOS analog circuit will usually have an offset voltage within the range of plus or minus 5mV if the layout design rules are followed; increasing the size of the differential pair at the output and input stages can reduce the Offset voltage, but the result of this design will make the input and output capacitance too high, seriously reducing the accuracy and speed of the circuit; therefore, many high-precision systems need to use electronic methods to eliminate mismatch; usually the automatic zero method needs to be used passive components such as capacitors to achieve mismatch compensation

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