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Locking detector of phase-locked loop (PLL) and detection method thereof

A technology of detectors and phase-locked loops, which is applied to the detection of lock-in detectors and the field of lock-in detectors

Active Publication Date: 2010-02-03
豪威国际控股有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This phenomenon is called "dead zone", which will directly introduce high-energy frequency spurs (spurs) into the output signal spectrum of the PLL. For those applications that require high spectral purity of the output signal, the appearance of spurs will become unacceptable

Method used

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  • Locking detector of phase-locked loop (PLL) and detection method thereof
  • Locking detector of phase-locked loop (PLL) and detection method thereof
  • Locking detector of phase-locked loop (PLL) and detection method thereof

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Embodiment 1

[0053] The invention discloses a phase-locked loop lock-in detector and its lock-in detection method. By introducing programmable technology in multiple places and rationally dividing the functional structure of the lock-in detector, the huge flexibility in the application of the lock-in detection circuit is finally realized. and portability.

[0054] Such as figure 1 As shown, the phase-locked loop PLL includes a phase frequency detector PFD, a charge pump CP, a low-pass filter LPF, a voltage-controlled oscillator VCO, and a frequency divider Divider. The frequency and phase detector PFD generates the output control signal UP and the control signal DN by comparing the phase difference between the reference clock Fin and the feedback clock Fdiv generated by the frequency division of the VCO to control the switch of the upper / lower current source of the charge pump CP; The DN signal also maintains logic "1" for a set time when there is no phase difference between Fref and Fdiv...

Embodiment 2

[0071] In this embodiment, the schematic diagram of the composition of the locking detector of the phase-locked loop is as follows figure 2 shown.

[0072] Since the time difference between the UP signal and the DN signal maintaining logic "1" indicates the phase difference between Fref and Fdiv, an exclusive OR gate circuit is used to collect the time when the UP signal and the DN signal are logic "1" alone. This time It is proportional to the phase difference between Fref and Fdiv. When one of the UP or DN signals is at high level and the other is at low level, the XOR gate outputs high level, thereby driving the charging resistor R behind it to charge the charging capacitor C. This charging process will be maintained until when the UP and DN signals are logic "1" at the same time, at this time the AND gate will generate a clock rising edge to drive the D flip-flop to sample the level on the capacitor to determine the difference between Fref and Fdiv Whether the phase dif...

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Abstract

The invention discloses a locking detector of a phase-locked loop (PLL) and a detection method thereof. The locking detector comprises an XOR gate, an AND gate, a charging resistor, a charging capacitor and a first trigger, wherein the XOR gate receives an UP signal and a DN signal; the output end of the XOR gate is connected with the input end of the first trigger by the charging resistor R and the charging capacitor C; and the AND gate receives the UP signal and the DN signal and generates a clock rising edge according to the UP signal and the DN signal to drive the first trigger to sample alevel of the charging capacitor C so as to judge whether a phase difference between Fref and Fdiv is small enough and judge the PLL is in an unlocked state or a locked state. The locking detector ofthe phase-locked loop (PLL) and the detection method thereof introduce programmable technologies in a plurality of places, reasonably divide the functional structure of the locking detector and finally realize the gigantic flexibility and the portability of the application of a locking circuit.

Description

technical field [0001] The invention relates to a phase-locked loop circuit, in particular to a lock detector of the phase-locked loop; moreover, the invention also relates to a detection method of the lock detector of the phase-locked loop. Background technique [0002] The English full name of the phase-locked loop is Phase-Locked Loop, referred to as PLL. A phase-locked loop circuit is a feedback circuit whose function is to synchronize the phase of the clock on the circuit with an external clock. Because the phase-locked loop can automatically track the frequency of the output signal to the frequency of the input signal, the phase-locked loop is usually used in a closed-loop tracking circuit. During the working process of the phase-locked loop, when the frequency of the output signal is equal to the frequency of the input signal, the output frequency signal and the input frequency signal maintain a fixed phase difference, that is, the phase of the output voltage and the...

Claims

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Application Information

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IPC IPC(8): H03L7/089H03L7/10
Inventor 衣晓峰
Owner 豪威国际控股有限公司
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