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Full digital phase-locked loop applying rapid frequency capture method

An all-digital phase-locked loop and frequency capture technology, applied in the automatic control of power, electrical components, etc., can solve the deterioration of the phase-locked loop, the output clock jitter performance of the phase-locked loop, the stability of the phase-locked loop system, and the locking time of the phase-locked loop Unsatisfactory and other issues

Active Publication Date: 2010-02-03
SOUTHEAST UNIV
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AI Technical Summary

Problems solved by technology

However, the increase in the bandwidth of the PLL will deteriorate the jitter performance of the PLL output clock and the stability of the PLL system, and the locking time of the PLL is not ideal, at least dozens of reference clock cycles

Method used

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  • Full digital phase-locked loop applying rapid frequency capture method
  • Full digital phase-locked loop applying rapid frequency capture method
  • Full digital phase-locked loop applying rapid frequency capture method

Examples

Experimental program
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Embodiment Construction

[0063] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0064] see image 3, the all-digital phase-locked loop of the fast frequency capture algorithm proposed by the present invention is provided with two loops of fast frequency capture and phase locking, and the two loops work alternately. First, the frequency capture is completed by the fast frequency capture loop, and then by A phase-locked loop completes precise locking. There are 4 counters in the figure, and the number of counters varies with the number of clocks with different phases that the numerical control oscillator can generate. The selected numerically controlled oscillator is a five-level loop numerically controlled oscillator, so five high-frequency clocks with different phases can be generated, named CLK[0], CLK[1], CLK[2], CLK[3] and CLK respectively [4]. CLK[0] is sent into the frequency divider matching the algorithm, CLK[1]...

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PUM

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Abstract

The invention relates to a full digital phase-locked loop applying a rapid frequency capture method for locking the frequency of the full digital phase-locked loop comprising a phase detection discriminator, a time-to-digit converter, a digital filter, a digital controlled oscillator and a frequency divider in a short time. The full digital phase-locked loop is characterized by comprising the following steps: finding a control word controlling the frequency of the digital controlled oscillator by a designed algorithm; and dividing a frequency output by the digital controlled oscillator which is controlled by the control word to obtain a divided-frequency clock with the frequency approximate to a reference clock frequency. The full digital phase-locked loop is provided with a rapid frequency capture loop and a phase-locked loop which alternately work, i.e. firstly, the rapid frequency capture loop finishes frequency capture, and then, the phase-locked loop finishes accurate locking.

Description

technical field [0001] The invention relates to an all-digital phase-locked loop used in an embedded chip, in particular to an all-digital phase-locked loop using a fast frequency acquisition method, which can greatly reduce the locking time of the phase-locked loop. Background technique [0002] With the development of integrated circuit deep submicron technology, people have higher and higher requirements on the performance and cost of embedded chips. The challenges of a series of issues such as high integration, portability, reliability and low cost have made the traditional analog phase-locked loop fully exposed its obvious disadvantages. Therefore, there is currently a trend to replace the voltage-controlled oscillator in the analog phase-locked loop with a digitally controlled oscillator (DCO), and replace the analog filter with a digital filter to form a new phase-locked loop called a full digital lock. phase ring. [0003] Such as figure 1 Shown is a commonly used...

Claims

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Application Information

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IPC IPC(8): H03L7/08
Inventor 陈鑫杨军刘新宁时龙兴
Owner SOUTHEAST UNIV
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