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Failure detection circuit of embedded dual processor system

A dual-processor and detection circuit technology, applied in electrical digital data processing, error detection/correction, instruments, etc., can solve problems such as CPU conflicts and high costs, reduce production costs, reduce circuit costs, and increase market competition force effect

Active Publication Date: 2009-12-30
ZHEJIANG SUPCON INSTR
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The purpose of the present invention is to provide a failure detection circuit for an embedded dual-processor system, so as to solve the shortcomings of the existing dual-CPU control system circuit cost is high, and conflicts between CPUs are easy to occur

Method used

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  • Failure detection circuit of embedded dual processor system
  • Failure detection circuit of embedded dual processor system
  • Failure detection circuit of embedded dual processor system

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Embodiment Construction

[0025] The principle of the present invention is that only one watchdog circuit is set in the control system of dual microprocessors, the watchdog circuit of the slave microprocessor is omitted, and the slave microprocessor is detected through the communication between the master and slave microprocessors. The operating state of the processor, and use the main microprocessor to control the power-on and power-off of the slave microprocessor, so as to achieve the purpose of system foolproof.

[0026] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0027] See figure 2 , which is a structural diagram of a failure detection circuit of an embedded dual-processor system according to an embodiment of the present invention. It includes a master microprocessor 201 , a slave microprocessor 203 , a watchdog circuit 205 and a power supply circuit 207 . The watchdog circuit 205 is connected to the main microprocessor 201 , the main...

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Abstract

The invention provides a failure detection circuit of an embedded dual processor system, comprising a main microprocessor, an auxiliary microprocessor, a watch dog circuit and a power circuit, wherein, the watch dog circuit is connected with the main microprocessor, which is used for monitoring the running state of the main microprocessor and resetting the main microprocessor in case of abnormality; the main microprocessor is connected with the auxiliary microprocessor via a communication circuit, carries out real-time communication with the auxiliary microprocessor and sends an enable signal to the power circuit according to the running state of the auxiliary microprocessor; the power circuit is respectively connected with the main microprocessor and the auxiliary microprocessor, which is used for supplying or breaking off the working voltage of the auxiliary microprocessor according to the enable signal sent by the main microprocessor. The invention can effectively prevent the abnormal state of the main and auxiliary microprocessors in the control system, ensures identical working sequence of main and auxiliary microprocessors, and has the advantages of simple structure, low cost of circuit and high reliability.

Description

technical field [0001] The invention relates to a detection circuit, in particular to a failure detection circuit of an embedded double processor system. Background technique [0002] As we all know, a single-chip microcomputer is compact, flexible, and highly scalable, and can form some powerful control systems (such as microcomputer excitation devices for generators, etc.). Conventional single-chip microcomputer control systems often use a CPU (processor), and then expand a series of peripheral auxiliary circuits to achieve the purpose of corresponding control. However, with the gradual improvement of the functions of the single-chip microcomputer control system, its hardware has become more and more complex, especially in systems with many input and output interfaces, tedious decoding and logic conversion must be performed when using a single CPU, and debugging is extremely difficult. Moreover, due to the increase in hardware functions, it is difficult for the processing...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05B23/02G06F1/24G06F11/00H02M3/04H03K17/78
Inventor 李堂忠佟志权管军
Owner ZHEJIANG SUPCON INSTR
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