High-speed parallel equalizer and equalizing method thereof

Abstract

The invention discloses a high-speed parallel equalizer and an equalizing method thereof, relating to the field of a digital receiver. The method comprises the following steps of: changing a carrier wave-recovered data which is sent by a front end receiver into parallel 2n lines; converting the data by means of frequency domain; filtering the wave of the data by means of equalizing in the frequency domain; outputting the wave-filtered data after being converted into frequency domain; selecting the latter n lines of output data according to the principle of circular convolution; extracting error information; converting the error information by means of frequency domain; and completing the update of a weight coefficient in the frequency domain, thereby completing a data-equalizing and a weight coefficient-updating process. The method is quite suitable for processing high-speed digital communication and conquers the limitation of hardware resources.

Description

technical field [0001] The invention relates to the field of digital communication, in particular to the field of digital receivers, in particular to a parallel equalizer for high-speed digital receivers and an equalization method thereof. Background technique [0002] When the signal is transmitted from the sending end to the receiving end, it will be affected by various effects such as nonlinearity, rain attenuation, and multipath, which will distort the transmitted signal, resulting in waveform distortion and causing intersymbol interference. The solution to this problem is to use equalization technology to compensate for signal distortion caused by channel parameter changes, offset channel signal transmission attenuation, and at the same time effectively combat intersymbol interference, reduce bit errors, and increase transmission rates. By using equalization technology to adjust the amplitude and phase of each frequency component of the received signal, the channel can ...

AI Technical Summary

Problems solved by technology

However, for high code rates, the processing of data by the demodulator is limited by the hardware speed of the FPGA, so parallel processing is necessary.

Then the data sent at the input end of the equalizer is in parallel. Using the traditional serial equalization algorithm in the past to equalize each channel, the effect is not good, because the data points used for equalization are not continuous.

Therefore, a parallel equalization algorithm must be used. Since the parallel algorithm is more complex than the serial algorithm, it is rare to see a practical high-speed parallel equalization algorithm implementation.

[0004] Existing high-rate parallel equalization algorithms, such as the "New Algorithm for High-Rate Data Equalizer Parallel Structure", equalize parallel data in the time domain. If high-order equalization is to be performed, the required multipliers will increase rapidly. It is beneficial to the realization of hardware; the patent "High-speed Digital Receiver Parallel Adaptive Blind Equalization Algorithm" applied by Tsinghua University, the application number is 200710064140.5, this method is also equalized in the time domain, firstly perform a 1:L channel serial-to-parallel conversion, Then perform unit delay processing to convert L-channel data into 2L-1-channel data, then perform L-channel parallel FIR filtering, and finally output the data through L:1 parallel-serial conversion, and the data sequence output by the equalizer is serial

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