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Frame synchronous byte recognition system based on FPGA and recognition method

A recognition system and frame synchronization technology, applied in the direction of digital video signal modification, TV, electrical components, etc., can solve the problems of insufficient reliability and long detection time, so as to improve efficiency, occupy less resources, and reduce the time required for detection Effect

Inactive Publication Date: 2009-08-26
SPACE STAR TECH CO LTD
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  • Abstract
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AI Technical Summary

Problems solved by technology

This technology is not equal to the synchronization time of different TS streams, which has the disadvantages of long detection time and insufficient reliability

Method used

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  • Frame synchronous byte recognition system based on FPGA and recognition method
  • Frame synchronous byte recognition system based on FPGA and recognition method
  • Frame synchronous byte recognition system based on FPGA and recognition method

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Embodiment Construction

[0032] Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

[0033] The present invention takes 188 bytes as an example to describe the FPGA-based frame synchronization byte recognition system and recognition method:

[0034] Such as figure 1 As shown, it is a simplified structural diagram of the FPGA-based frame synchronization byte recognition system of the present invention. As can be seen from the figure, the FPGA-based frame synchronization byte recognition system of the present invention includes a monitoring state judgment module, a data byte counting module, and a synchronization byte occurrence Position recording module, five modules of synchronous byte quantity counting module and data frame quantity indicating module, wherein the data byte counting module counts the data bytes of the current data frame of the TS stream, and records each byte in the current data frame The position within, ...

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Abstract

The invention relates to a frame synchronous byte recognition system based on FPGA and a recognition method, wherein, the synchronous recognition method comprises the steps as follows: counting the data byte of the current data frame of TS flow and recording the position of each byte in the current data frame; judging whether the current data frame is a first frame; recording the position of the byte with the value of 0X47 in the current data frame, and labeling; recording the number of the positions of the bytes labeled as 1 in the current data frame; entering a monitoring state when the number of the position of the byte labeled as 1 is one in the current data frame, otherwise, entering a next frame. The synchronous byte recognition method of the invention is fast and reliable and easily achieved, and can improve the synchronous speed and reduce the loss of effective data and data processing time of TS flow.

Description

technical field [0001] The invention relates to an FPGA-based frame synchronization byte recognition system and recognition method. Background technique [0002] DVB-RCS is a DVB-S system with a satellite return channel. The so-called DVB-S is a digital satellite broadcasting standard that conforms to the European telecommunications standard ETS 300 421. Adopted by many countries, it has become the mainstream standard of digital satellite broadcasting. The frame structure, channel coding method and modulation method of digital signals (including digital video, digital audio and data signals) in digital satellite broadcasting are described in detail in the ETS 300 421 standard. This standard adopts the ISO / IEC13818 MPEG-2 standard officially launched in 1994 as its information source compression coding scheme. [0003] There are two transmission formats for MPEG-2TS stream, one is 188-byte format (without RS code), and the other is 204-byte format (with RS code). This arti...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N7/26H04N19/102
Inventor 闫峥邹光南李申阳
Owner SPACE STAR TECH CO LTD
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