Method and device for verifying SoC (system on a chip) chips

Abstract

The invention relates to the field of SoC chips, in particular to a method and a device for SoC chips, which is used for solving the problem that the occurrence of random vectors and control difficulty are increased because each verification needs to be compiled again when different functions of the same SoC chip are verified in the prior art. The method of the embodiment of the invention comprises the following steps: setting a configuration file of an SoC chip, wherein the configuration file comprises the basic information of the SoC chip and constraint conditions of modules in the SoC chip; according to received instructions, determining the modules referring to the functions of the SoC chip which need to be verified; according to the basic information, the constraint conditions of the determined modules and module function data in the instructions, generating a random test vector; and according to the random test vector, verifying the SoC chip. The embodiment of the invention has the advantages of reducing the complexity of constructing verification systems and maintenance difficulty, increasing the reusability of verification components, lowering verification difficulty and saving time.

Description

technical field [0001] The present invention relates to the field of System on a Chip (SoC) chips, in particular to a method and device for SoC chip verification. Background technique [0002] As SoC chip design becomes increasingly complex, verification becomes a key link in the SoC chip design process. Before a design is synthesized, logic function verification is first performed to ensure the functional correctness of the module or chip. Common functional verification mainly adopts a bottom-up verification strategy, which can be divided into two stages: module-level verification and system-level verification. [0003] Most of the traditional verification methods communicate directly with the SoC chip to be verified on the signal-level interface, that is, directly drive the pins of the SoC chip with excitation, and verify the design function by checking the value and change of the interface signal. The abstraction level of this method is low, and the development of the v...

AI Technical Summary

Problems solved by technology

[0018] Embodiments of the present invention provide a SoC chip verification method and device, which are used to solve the problem in the prior art that when verifying different functions of the same SoC chip, each verification needs to be recompiled, which increases the generation and control of random vectors. problem of difficulty

[0019] The embodiment of the present invention provides a method and device for SoC chip verification, and further solves the problems of complex test system construction, long construction time, poor reusability, and difficult maintenance

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