Electrostatic discharging protection circuit

Abstract

A static discharge protection circuit comprises: a step-down module that is coupled between a first voltage level and a second voltage level, wherein the first voltage level is higher than the second voltage level; a grid trigger switch that is coupled between the first voltage level and the second voltage level; and a detection circuit that is coupled with the grid trigger switch and used for detecting static discharge events so as to control the grid trigger switch.

Description

technical field [0001] The present invention relates to an electrostatic discharge protection circuit, in particular to an electrostatic discharge protection circuit with high sustain voltage. Background technique [0002] figure 1 A prior art electrostatic discharge protection circuit 100 is shown. Such as figure 1 As shown, the ESD protection circuit 100 includes a detection circuit 101 and an NMOS transistor 103 . The detection circuit 101 is used to detect an ESD event to control the NMOS transistor 103, and the NMOS transistor 103 is used as a switch. Generally speaking, the detection circuit 101 includes a circuit composed of a capacitor and a resistor, and uses the delay characteristics of the capacitor and resistor to control the NMOS transistor 103 according to the electrostatic discharge event. [0003] However, such a structure will cause the holding voltage of the NMOS transistor 103 to be lower than V when an ESD event occurs. DD , so that the NMOS transist...

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Problems solved by technology

[0003] However, such a structure will cause the holding voltage of the NMOS transistor 103 to be lower than V when an ESD event occurs. DD , so that the NMOS transistor 103 is latch-up

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