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Computer architecture scheme parallel simulation optimization method based on cluster system

A technology of architecture and cluster system, applied in the direction of computer, digital computer components, computing, etc., can solve problems such as simulation optimization of computer architecture design schemes that have not yet been seen

Inactive Publication Date: 2009-06-24
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] According to the retrieval of patent documents, there is no relevant report in the previous patents and documents that realizes the simulation optimization of computer architecture design schemes based on cluster parallel computer systems by means of throughput calculation.

Method used

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  • Computer architecture scheme parallel simulation optimization method based on cluster system
  • Computer architecture scheme parallel simulation optimization method based on cluster system
  • Computer architecture scheme parallel simulation optimization method based on cluster system

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Embodiment Construction

[0095] figure 1 It is the physical structure diagram of the cluster system built in the first step of the invention. According to the function, the nodes of the cluster are divided into master nodes and simulation nodes. Both master nodes and simulation nodes contain processors, main memory, disks, and network interface devices. The master control node is equipped with input and output terminals. The master control node and the simulation node are connected through an interconnection network device, and the interconnection network can be Ethernet, Myrinet, Infiniband, or other types of networks.

[0096] figure 2 It is a software deployment diagram of the cluster system of the present invention. Operating system software, network TCP / IP software, remote command execution software, global configuration program, simulation configuration file generation program, task scheduler and result analysis program are installed on the master control node. Wherein the first three are ...

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Abstract

The invention discloses a parallel method for simulating and optimizing the computer architecture scheme based on a cluster system, and aims to provide a parallel method for simulating and optimizing the design scheme of the computer architecture. The technical scheme is that a parallel computer system which consists of a main control node and simulation nodes and is provided with a remote command execution environment is firstly built, and a global configuration program, a simulated configuration file generating program, a task dispatching program and a result analyzing program are arranged on the main control node, wherein, the global configuration program is used for arranging global configuration; the simulated configuration file generating program is used for generating all simulated configuration files; the task dispatching program distributes simulation evaluation tasks to each node, controls each simulation node and performs simulation evaluation; and the result analyzing program searches simulation result files sent from the simulation nodes for statistics, screens out optimal configuration parameter values, and outputs a report. By adopting the invention, the time for evaluation and optimization can be reduced, and the selection accuracy is improved.

Description

technical field [0001] The invention relates to a computer system simulation method, in particular to a parallel simulation evaluation of different configuration schemes of the computer architecture by using a cluster parallel computer system as a host machine, so as to optimize the design scheme of the computer architecture. Background technique [0002] In the process of computer system development, it is usually necessary to evaluate various configurations of computer architecture, so as to obtain the optimal design scheme under the constraints of technology and cost. For example, important parameters such as the number of on-chip processor cores and the interconnection structure, on-processor cache (Cache) size, block size, and associativity of the on-chip multiprocessor system (CMP) all have certain possible ranges. Different values ​​may lead to great changes in performance, and it is necessary to comprehensively consider the values ​​of these parameters in order to ob...

Claims

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Application Information

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IPC IPC(8): G06F17/50G06F9/455G06F15/173
Inventor 车永刚徐传福王勇献王正华陆平静曹维方建滨翁玉芬
Owner NAT UNIV OF DEFENSE TECH
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