Three-dimensional quantum well CMOS integrated device and preparation method thereof
A technology of integrated devices and quantum wells, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problem of low speed of three-dimensional integrated circuits, and achieve the goal of ensuring AC and DC electrical performance, improving performance, and improving performance Effect
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Embodiment 1
[0040] Embodiment 1: The steps for fabricating a three-dimensional quantum well CMOS integrated device with a 90nm conductive channel are as follows:
[0041] (1) Select SSOI substrate with stress> 1Gpa;
[0042] (2) On the SSOI substrate, use oxidation-photolithography source, drain, gate region-gate oxidation-deposition of polysilicon-photolithography of polysilicon and diffusion layer contact hole-deposition of polysilicon-photolithography of polysilicon-phosphorus implantation-low temperature deposition Product SiO 2 -Lithography lead hole-Polysilicon wiring-Low temperature deposition of SiO 2 Dielectric layer, fabricating strained Si nMOSFET device structure with 90nm conduction channel and interconnecting each other to complete the lower active layer structure;
[0043] (3) Depositing SiO on the surface of the above active layer 2 Dielectric layer
[0044] (4) Surface oxidation of the cleaned n-type Si wafer as the upper base material;
[0045] (5) Use ion implantation process to...
Embodiment 2
[0052] Embodiment 2: The steps for fabricating a three-dimensional quantum well CMOS integrated device with a 130 nm conductive channel are as follows:
[0053] (1) Select SSOI substrate with stress> 1Gpa;
[0054] (2) On the SSOI substrate, use oxidation-photolithography source, drain, gate region-gate oxidation-deposition of polysilicon-photolithography of polysilicon and diffusion layer contact hole-deposition of polysilicon-photolithography of polysilicon-phosphorus implantation-low temperature deposition Product SiO 2 -Lithography lead hole-Polysilicon wiring-Low temperature deposition of SiO 2 Dielectric layer, fabricating strained Si nMOSFET device structure with 130nm conduction channel and interconnecting to complete the lower active layer structure;
[0055] (3) Depositing SiO on the surface of the above active layer 2 Dielectric layer
[0056] (4) Surface oxidation of the cleaned n-type Si wafer as the upper base material;
[0057] (5) Use ion implantation process to implant...
Embodiment 3
[0064] Embodiment 3: The steps of fabricating a three-dimensional quantum well CMOS integrated device with a 65nm conductive channel are as follows:
[0065] (1) Select SSOI substrate with stress> 1Gpa;
[0066] (2) On the SSOI substrate, use oxidation-photolithography source, drain, gate region-gate oxidation-deposition of polysilicon-photolithography of polysilicon and diffusion layer contact hole-deposition of polysilicon-photolithography of polysilicon-phosphorus implantation-low temperature deposition Product SiO 2 -Lithography lead hole-Polysilicon wiring-Low temperature deposition of SiO 2 Dielectric layer, fabricating strained Si nMOSFET device structure with 65nm conduction channel and interconnecting to complete the lower active layer structure;
[0067] (3) Depositing SiO on the surface of the above active layer 2 Dielectric layer
[0068] (4) Surface oxidation of the cleaned n-type Si wafer as the upper base material;
[0069] (5) Use ion implantation process to implant hyd...
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