Staggered offset stacking encapsulation construction having multistage omnibus bar in conductive wire support

Abstract

The invention provides an encapsulated structure which is provided with a multisection type bus bar and stacked in a staggered manner in a lead frame. The encapsulated structure comprises the lead frame which is composed of a plurality of oppositely arranged inner pin groups, a plurality of outer pin groups and a chip support plate, wherein, the chip support plate is disposed among the plurality of oppositely arranged inner pin groups, therefore, a height difference is produced between the plurality of oppositely arranged inner pin group and the chip support plate; a stack-type chip device is formed by stacking a plurality of chips, and disposed on the chip support plate; the plurality of chips are electrically connected with the plurality of oppositely arranged inner pin groups; and the encapsulating body is used for wrapping the stack-type chip device and the lead frame, wherein the lead frame includes at least a bus bar which is disposed between the plurality of oppositely arranged inner pin groups and the chip support plate, and formed in the manner of multiple sections.

Description

technical field [0001] The present invention relates to a multi-chip stacking package structure with staggered offset, in particular to a multi-chip stacked package structure with a staggered offset (zigzag) stacking structure. Background technique [0002] In recent years, three-dimensional (3D) packaging is being carried out in the back-end process of semiconductors, in order to use the least area to achieve relatively large semiconductor integration (Integrated) or memory capacity. In order to achieve this goal, a chip stacked method has been developed to achieve a three-dimensional (Three Dimension; 3D) package at this stage. [0003] In the prior art, the chip stacking method is to stack multiple chips on a substrate, and then use a wire bonding process to connect the multiple chips to the substrate. Figure 1A It is a schematic cross-sectional view of an existing stacked chip package structure with the same or similar chip size. Such as Figure 1A As shown, the existi...

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Problems solved by technology

Figure 1D It discloses an alternately stacked packaging structure. Obviously, it uses the height between the chips to replace the spacers, so that the packaging density can be increased. However, this packaging structure still has troubles in the process, that is, it must first complete two After the connection of two chips, the first metal wire connection can be carried out, and then the other two chips can be connected, and then the second metal wire connection can be carried out. Therefore, when the number of chips increases, the manufacturing process is relatively complicated and difficult.

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