Method and apparatus for implementing hardware level verification

Abstract

The invention discloses a method and a device for realizing hardware level verification. The device comprises a basic development and verification board and an extended development and verification board which are connected with each other through an AMBA bus of a high-quality microprocessor bus framework, wherein the basic development and verification board reads and writes a CPU register through an EJTAG interface of a reinforced joint test action group and executes CPU IP verification, and the basic development and verification board and the extended development and verification board execute the CPU IP verification and SOC (system on a chip) verification through the AMBA bus. The method and the device have the advantages that: firstly, structures of the basic development and verification board and the extended development and verification board not only can conveniently realize design and development and functional verification of an SOC but also can complete the development and verification work of IP and particularly CPU IP; secondly, the cost can be reduced; and thirdly, system correction and extension are easier and realization is flexible and convenient.

Description

technical field [0001] The invention relates to a system-on-chip (SOC, System-on-Chip) technology, in particular to a hardware-level verification method and device capable of simultaneously realizing SOC verification and IP verification. Background technique [0002] In today's integrated circuit (IC, Integrated circuit) design field, SOC has suddenly emerged and developed extremely rapidly. The SOC design based on silicon intellectual property (IP) is different from the traditional application-specific integrated circuit (ASIC, Application Specific Integrated Circuit) design. Its design cycle is short and it can better meet the needs of the market. Like the previous ASIC design, SOC also faces the problem of Field Programmable Gate Array (FPGA, Field Programmable Gate Array) hardware-level verification. The current FPGA development and verification is mainly based on a single development board, that is, a single FPGA, and there are also multiple FPGAs, which are usually or...

AI Technical Summary

Problems solved by technology

The connection of the two FPGAs uses the corresponding CPU bus or a custom bus instead of the SOC system bus, such as the Advanced Microcontroller Bus Architecture (AMBA, Advanced Microcontroller Bus Architecture) bus, which makes the system run at a low speed.

In this case, since the bus structure connecting the two FPGAs is different from the SOC system bus, SOC verification cannot be truly realized.

[0006] In summary, the solutions provided by the prior art cannot simultaneously provide effective SOC verification and IP verification in the SOC

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