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Low density parity check code implementing apparatus

A low-density parity and parity check matrix technology, applied in the field of codec, can solve the problems of high coding complexity, large storage space, and large storage capacity of LDPC codes

Inactive Publication Date: 2008-12-31
NUFRONT MOBILE COMM TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0015] From a practical point of view, an important factor that restricts the wide application of LDPC codes is: the storage capacity of the sparse parity check matrix and the non-sparse generator matrix is ​​too large, resulting in a very large storage space when using LDPC codes for encoding. Big
In addition, the high coding complexity of traditional LDPC codes is also an important factor restricting its wide application.
Due to the above shortcomings, LDPC codes have not been widely used in practical applications.

Method used

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Embodiment 1

[0062] In this embodiment, the rule (4608, 2304) LDPC code is taken as an example for illustration. The code length N of the regular LDPC code to be realized in this embodiment is 4608, the row weight ρ=6, and the code rate v=1 / 2. It can be seen from the corresponding relationship between the code rate, the code length and the number of check equations that the number of check equations in the check matrix in this embodiment is M=4608-2304=2304. In addition, in this embodiment, the implementation process of the above-mentioned quasi-cyclic LDPC code will be described by taking a cyclic sub-matrix with 72 rows×72 columns as the minimum cyclic unit as an example.

[0063] The method flow chart of this embodiment and figure 2 The flow chart of the exemplary method of the present invention shown is similar, see figure 2 , the realization method of QC-LDPC code in the present embodiment comprises the following steps:

[0064] In step 201, according to the preset code length, c...

Embodiment 2

[0092] In this embodiment, an irregular LDPC code with the same row weight (4608, 2304) is taken as an example for illustration. The code length N of the regular LDPC code to be realized in this embodiment is 4608, the row weight ρ=7, and the code rate v=1 / 2. From the correspondence between the code rate, the code length and the number of check equations, it can be known that this The number of check equations in the check matrix of the embodiment is M=4608-2304=2304. In addition, in this embodiment, the same as the first embodiment, a 72×72 cyclic sub-matrix is ​​taken as an example to illustrate the implementation process of the above-mentioned quasi-cyclic LDPC code.

[0093] The method flow chart of this embodiment and figure 2 The flow chart of the exemplary method of the present invention shown is similar, see figure 2 , the realization method of QC-LDPC code in the present embodiment comprises the following steps:

[0094] In step 201, according to the preset code ...

Embodiment 3

[0120] In this embodiment, an irregular LDPC code with (4608, 3096) row weights is taken as an example for illustration. The code length N of the regular LDPC code to be realized in this embodiment is 4608, the row weight ρ=12 or 13, and the code rate v=43 / 64, as can be seen from the correspondence between the code rate, the code length and the number of check equations , the number of check equations in the check matrix in this embodiment is M=4608-3096=1512. In addition, in this embodiment, the same as the first embodiment, a 72×72 cyclic sub-matrix is ​​taken as an example to illustrate the implementation process of the above-mentioned quasi-cyclic LDPC code.

[0121] The method flow chart of this embodiment and figure 2 The flow chart of the exemplary method of the present invention shown is similar, see figure 2 , the realization method of QC-LDPC code in the present embodiment comprises the following steps:

[0122] In step 201, according to the preset code length, ...

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Abstract

The invention discloses a device for realizing a low-density parity check code, which comprises a memory module used for storing digit sequences, a check-matrix generating module used for constructing a parity check matrix of LDPC codes by adopting a cyclic shift mode according to the digit sequences, and a code word generating module which transforms the input data into LDPC code words by the parity check matrix. The adoption of the device of the invention can reduce the storage space needed for storing the parity check matrix.

Description

[0001] This application is a divisional application of an application with a filing date of November 17, 2006, an application number of 200610145182.7, and an invention title of "a class of low-density parity-check code realization method and device". technical field [0002] The invention relates to the coding and decoding technology of the digital communication system, in particular to a kind of low-density parity check code realization device. Background technique [0003] Due to the influence of factors such as random noise and multipath fading in wireless transmission, various errors often occur in data transmission in communication systems, especially in digital multimedia broadcasting systems, where data volume is large, bandwidth is limited, and various bursts There is a lot of interference, which makes the reliability problem of data transmission more prominent. [0004] Typically, channel coding is used to ensure reliable communication in noisy communication channe...

Claims

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Application Information

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IPC IPC(8): H04L1/00H03M13/11H03M13/00
Inventor 鲍东山王加庆
Owner NUFRONT MOBILE COMM TECH
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