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Paralleling microprocessor and its realization method

A microprocessor, technology for implementing methods, applied in the direction of architecture with a single central processing unit, electrical digital data processing, digital data processing components, etc.

Active Publication Date: 2008-12-31
NEUSOFT MEDICAL SYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since INMOS was acquired by STMicroelectronics in 1989, IMS T400 series and T800 series parallel microprocessors are no longer available to the market, making IMS T400 series fixed-point parallel microprocessors and IMS T800 series floating-point parallel microprocessors in the life cycle terminated state

Method used

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  • Paralleling microprocessor and its realization method
  • Paralleling microprocessor and its realization method
  • Paralleling microprocessor and its realization method

Examples

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example 1

[0180] Example 1: If before decoding, the memory code is 41, then after decoding, the operation code is x0040; the operand is x00000001. If before decoding, the memory code sequence is 22, 23, 24, 53, then after decoding, the operation code is x0050; the operand is x00002345. If before decoding, the memory code sequence is 23, FB, then after decoding, the operation code is x23FB; the operand is x00000000.

example 2

[0181] Example 2: If x33F6BA21 stored at address x80000070 and 72FA2446 stored at address x80000074, the following opcode, operand and address (Iptr) of the next instruction will be obtained after decoding:

[0182] Opcode x00B0, operand x0000001A, next instruction address x80000072;

[0183] Opcode x00F6, operand x00000000, next instruction address x80000073;

[0184] Opcode x0030, operand x00000003, next instruction address x80000074;

[0185] Opcode x0040, operand x00000006, next instruction address x80000075;

[0186] Opcode x24FA, operand x00000000, next instruction address x80000077;

[0187] Opcode x0070, operand x00000002, next instruction address x80000078.

[0188] The decoding unit 12 writes the operation codes and operands into the instruction queue in sequence, and writes the address of the next instruction into the instruction pointer queue 17 .

[0189] 3. Instruction queue and instruction pointer queue unit (Instruction Queue & Iptr Queue)

[0190] Both th...

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Abstract

The invention relates to a parallel microprocessor and a corresponding realization method which are based on FPGA development. The parallel microprocessor comprises a CPU which is a 32-bit fixed-point CPU formed by a fetch decoding unit, a process management unit and an integer instruction execution unit; a communication module formed by a plurality of units of LINK channels and In / Out controllers; an arbitration controller used for arbitrating internal and external address buses and a data bus of the CPU; an external memory interface used for providing reading / writing time-sequence logic for an external memory; an interruption / time-sequence controller used for providing timing and interruption for the CPU; an internal memory used for providing the instructions of the CPU and quickly accessing data. The CPU is also provided with a floating point unit (FPU) combining the 32-bit fixed-point CPU to form a 64-bit floating point CPU. The 32-bit fixed-point parallel microprocessor and the 64-bit floating point parallel microprocessor provided by the invention work stably, bring convenience for system modification and debugging, accelerate verification speed and provide a low-cost operation platform for programs written in OccamII language.

Description

technical field [0001] The invention relates to the technical field of microprocessors, in particular to a parallel microprocessor developed based on FPGA and supporting parallel programming language and its implementation method. Background technique [0002] The original hardware platform supporting the parallel programming language Occam II is the IMS T400 series parallel fixed-point Transputer microprocessors and the IMST800 series parallel floating-point Transputer microprocessors successively launched by the British INMOS company after 1984. IMS T400 series parallel fixed-point microprocessors include T414 and T425 two microprocessors, IMS T800 series floating-point microprocessors include T801 and T805 two parallel microprocessors, IMS T400 and T800 series parallel microprocessors respectively support all Occam II language fixed-point instruction set and floating-point instruction set. However, since INMOS was acquired by STMicroelectronics in 1989, IMS T400 series a...

Claims

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Application Information

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IPC IPC(8): G06F15/78G06F9/30G06F9/48G06F7/57
Inventor 史建华王君杰孙容李海泉吴林王鹏张丙春孙佳音
Owner NEUSOFT MEDICAL SYST CO LTD
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