Elastic buffering mechanism and method for compensating clock diversity

Abstract

The invention relates to an elastic buffer device which comprises a plurality of FIFO (first in first out) units used for writing in and reading the data of the data packet of corresponding data channels; a plurality of FIFO unit controllers used for controlling the reading or writing of pointers to write the data in or read the data from the corresponding FIFO units, calculating the distance of the reading and writing pointers according to the detected position of the reading and writing pointers of the corresponding data channels, adjusting the position of the reading pointer according to the preset distance scope of the reading and writing pointers, counting the data head identifiers of the received data packet of the corresponding data channels, notifying the counting result to a multi-channel deflection controller, and adjusting the position of the reading pointer of the FIFO unit of the data channel according to the feedback of the multi-channel deflection controller; the multi-channel deflection controller used for carrying out comprehensive analysis according to the counting result of data head identifiers sent by each FIFO unit controller, and transmitting feedback signals to each FIFO unit controller, thus causing the area of PCI Express to be comparatively small.

Description

technical field [0001] The invention relates to an elastic buffer device located at a physical interface of a high-speed peripheral component interconnection (PCI Express, Peripheral Component Interconnect) and a method for using the elastic buffer device to compensate clock differences. Background technique [0002] High-speed peripheral component interconnection (PCI Express, Peripheral Component Interconnect) is an interconnection technology between chips and a board expansion interface technology. Compared with the shared parallel architecture of traditional PCI and earlier computer buses, PCI Express uses a point-to-point serial connection (serial interface) between devices. In this way, each device is allowed to have its own dedicated connection, which is exclusive and does not need to request bandwidth from the entire bus. At the same time, using the serial connection characteristics will easily increase the data transmission speed to a very high frequency. Achieve t...

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Problems solved by technology

[0004] The problem to be solved by the present invention is the larger problem of PCI Express design area in the prior art

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