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Analog-to-digital converter

An analog-to-digital converter and converter technology, applied in analog-to-digital conversion, code conversion, instruments, etc., can solve the problems of long time, large false signal, large area occupied by capacitors, etc. loss, the effect of improving the signal-to-noise ratio

Inactive Publication Date: 2008-09-10
ANALOG DEVICES INC
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this is not always appropriate as larger capacitors take up more area in the integrated circuit and take longer to sample the input signal as they cause larger glitches at the circuit driving the ADC, Thus these circuits take longer to stabilize

Method used

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Examples

Experimental program
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Effect test

Embodiment Construction

[0018] figure 1 The input stage of a switched capacitor based analog-to-digital converter is schematically shown. In general, the input stage includes m+1 capacitors C0-Cm, one of the plates of said capacitors (such as figure 1 The uppermost plate shown in ) is connected to a common lead 10 which is connected to the inverting input 12 of a comparator 14 . The non-inverting input 16 of comparator 14 is connected to ground. The second plate of each of the capacitors C0-Cm (as figure 1 The bottommost plate shown in ) is connected to the respective electronic switches S0-Sm. The switches S0-Sm are independently controllable to connect their associated capacitors to the input node 20 so that the capacitors can be charged to the input voltage Vin. Capacitors C0 to Cm can also be switched to a positive reference voltage Vref+ or a negative reference voltage Vref- (typically ground). Conductor 10 may also be connected to ground through an electronically controllable switch 22 whi...

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PUM

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Abstract

When the least significant bit LSB is confirmed, the normal SAR conversion is completed. A first test is represented. In the invention, N additional bits are also confirmed. Each additional bit represents a correction test. The result obtained by adding the result after each additional correction test to the conversion result after a (first) bit test when the last bit is normal is taken as the effective result. The last result is obtained by adding N+1 results together. Because the N+1 results are confirmed in different conditions, the effect of the noise of the comparator is reduced. The additional benefit of the method is obtaining a higher resolution result. For an example, the 16-bit converter which has three additional + / -0.5 bit correcting bit tests can generate a 18-bit conversion result when four results are added.

Description

technical field [0001] The present invention relates to analog-to-digital converters, in particular to analog-to-digital converters including circuitry for improving the signal-to-noise ratio by obtaining multiple conversion results without causing a proportional decrease in throughput. Background technique [0002] In an ideal noise-free world, any analog signal supplied to an analog-to-digital converter (ADC) would be accurately digitized to whatever resolution the converter's designer desires. However, in the real world, the performance of an analog-to-digital converter is limited by many factors. One of these constraints is self-generated noise within the analog-to-digital converter. Many analog-to-digital converters use switched capacitor arrays to perform dual functions as sampling capacitors and digital-to-analog converters during successive approximation analog-to-digital conversion. [0003] The signal-to-noise ratio SNR of an analog-to-digital successive approxim...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/06H03M1/46
CPCH03M1/468H03M1/0697
Inventor 克里斯托弗·彼得·赫里尔加里·罗伯特·卡罗
Owner ANALOG DEVICES INC
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