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Inner pin joint packaging

A technology of inner pins and pins, which is applied in the field of semiconductor packaging structures, can solve the problems of inability to complete eutectic bonding consistently, insufficient eutectic strength of thick legs, tin overflow of thin legs, etc.

Inactive Publication Date: 2008-07-30
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] It is worth noting that the time required for eutectic bonding between thick legs / thin legs and bumps is different, and the eutectic bonding process cannot be completed consistently. If the time required for eutectic bonding between thin legs and bumps is matched, thick The feet may have insufficient eutectic strength. If the eutectic time required for the thick feet is matched, the thin feet may overflow tin, and the inconsistent strength of the eutectic bonding between the leads and bumps will affect the reliability of the chip packaging structure.

Method used

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Examples

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Embodiment Construction

[0014] image 3 It is a top view of an embodiment of a pin-bonded chip package structure in the present invention. Please refer to image 3 , the internal pin bonding package 200 includes a chip 202 , a flexible board 210 , and pins 222 and 224 disposed on the flexible board 210 and electrically connected to the chip 202 . In this internal pin bonding package 200, the gold bumps or other solder bumps on the chip 202 are first completed, and the pins 222, 224 and the solder mask 230 on the flexible board 210 are completed, and then bonded by thermocompression or In the way of ultrasonic bonding, the bumps 204a, 204b on the chip 202 are electrically connected to the inner ends of the pins 222, 224 by gold-tin eutectic bonding. Although the present invention is described with a tape carrier package (TCP, tape carrier package) flexible board or a film-on-film (COF, chip on film) flexible board used in the tape automatic bonding process as a preferred example, those skilled in th...

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Abstract

The invention discloses an inner pin bonding package, which is suitable for bonding a chip on a soft panel by using tape automated bonding technology. The inner lead bonding package comprises a chip, the soft panel and a plurality of pins arranged on the soft panel and extended to a chip bonding section. The chip includes a bump eutectically bonded with the pins, and the pins include a first pin and a second pin, wherein the first pin includes a first eutectic-bonding region with the same width as that of the first pin at one end corresponding to the bump, and the second pin includes at least one groove at one end corresponding to the bump to form a second eutectic bonding region with a smaller width than that of the second pin. Accordingly, the eutectic bonding area between the first / second pin and the bump is uniformized. Accordingly, the inner pin bonding package process can be achieved in one step without causing the problems of poor bonding strength or solder wicking.

Description

technical field [0001] The present invention relates to a semiconductor packaging structure, and in particular to a packaging structure in which a chip is bonded to a flexible board with inner pins. Background technique [0002] In the prior art, tape automatic bonding (TAB, tape automatic bonding) is used for the chip packaging process. After the circuit on the flexible board and the bump process on the chip are completed, thermal compression is used. Inner lead bonding (ILB, inner lead bonding) is carried out in a way, so that the bumps on the chip and the inner leads on the flexible board are electrically connected by eutectic bonding. Next, use packaging resin to seal the circuits of the chip and the inner pins on the flexible board, and perform outer lead bonding (OLB, outer lead bonding) after electrical testing. Wherein, the outer pins are formed by the inner pins on the flexible board extending outwards, and the outer pins are used to electrically connect the flexib...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/488H01L23/498
CPCH01L2224/50
Inventor 何政良杨伟
Owner CHIPMOS TECH INC
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