Double-port access single dynamic memory interface

Abstract

The invention relates to a computer interface, in particular to an interface of a single dynamic memory with dual ports access. The invention eliminates the defects in the aspects of cost, memory capacity, system performance, usability, etc. existing in adopting dual port RAM device as a share memory and adopting time-sharing multiplexing technology of a bus to access to the share memory. The invention comprises a logic arbitration module, a sequence command interface module of a processor 1, a data caching module of the processor 1, a sequence command interface module of a processor 2, a data caching module of the processor 2, an interface control module of the dynamic memory, an initialization module and a refreshing module. The interface facilitates two or more processors simultaneously access to the dynamic memory in parallel; when one processor accesses to the share dynamic memory, another processor can begin access to the same dynamic memory without waiting the present processor to finish the access to the memory; the time required by the response of the memory to the access of the processor is further reduced, thereby enhancing the system performance.

Description

Technical field [0001] The present invention relates to a computer interface, in particular to an interface between a processor and a memory, and is specifically an interface for dual-processor ports to access a single dynamic memory. Background technique [0002] In recent years, shared memory in multiprocessor systems has been a research hotspot. Currently, there is only one access port to the shared memory, which increases the possibility of conflicts in the access of this shared memory by the multi-processor. When two or more processors access the memory, only one processor can access the memory, and the other processors are in a waiting state, that is, each processor cannot access the memory in parallel. In order to solve this problem, the currently popular technologies mainly include: the use of dual-port RAM devices and the time division multiplexing technology of the bus. The above methods have more or less defects in cost, memory capacity, system performance, and ease of...

AI Technical Summary

Problems solved by technology

However, this patent also uses fixed time slots to process read and write requests of multiple processors in a time-sharing manner, and requires the processors to access at the access timing of the dynamic memory (DRAM), which requires the bandwidth of the memory to be much larger than the processor port bandwidth, which is a very unfavorable limitation for applications

Moreover, at present, some processors cannot directly access DRAM directly, and an additional memory controller is required, which is not conducive to application

[0005] According to the above analysis, there is currently no shared storage control system (interface) for the existing dynamic memory (such as DDR SDRAM, DDR2SDRAM, etc.) as a shared memory in the market to achieve high performance, large capacity, low cost, and flexibility

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