Safe JTAG connection identification system and identification method

Abstract

The invention relates to the technical field of safety control of a chip JTAG test port, in particular to a safe JTAG connection authentication system and an authentication method thereof. The connection authentication system is equipped between a JTAG test port and a chip to be tested and composed of an access module and an authentication module, which have interactive interfaces. The authentication method comprises (A) one side of the access module and the authentication module gives an authentication request, the other side generates a random number RN; (B) the access module calculates an authentication X' to SN by using a local private key K', and transmits X' to the authentication module; (C) the authentication module calculates an authentication X to RN by using a local private key K; (D) the authentication module compares X and X' and decides whether to open a TAP port at chip end; (E) the authentication module returns the authentication result to the access module. The invention can achieve JTAG port automatic identification of a legal access object and starting or closing JTAG function with simple manner, so as to achieve the purpose of preventing internal logic of the chip being stolen.

Description

technical field [0001] The invention relates to the technical field of security control of a chip JTAG test port, in particular to a safe JTAG connection authentication system and an authentication method thereof. Background technique [0002] The JTAG port is one of the important ways to test the operation status of the internal port logic function after the chip is packaged. It plays an important role in the chip development process and later inspection and maintenance. Usually, the JTAG connection method of the chip is as follows figure 1 As shown, the computer is directly connected to the JTAG interface on the chip side through the test interface. JTAG is mainly connected through the test access port (TAP), which contains 5 ports, namely test clock (TCK), test mode selection (TMS), test data input (TDI), test data output (TDO) and Test the reset signal (TRST). [0003] Since the logic inside the chip can be directly read from the external pins of the chip through the ...

AI Technical Summary

Problems solved by technology

But the disadvantage is that it is cumbersome to operate. Before each test, you need to enter the password to open the JTAG function, and then close the JTAG function after the test.

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