Processor

Abstract

A processor (100) includes an ordinary instruction buffer (122) for storing and supplying one or more instructions fetched from an instruction cache (10), a TAR instruction buffer (123) for storing the one or more instructions fetched from the instruction cache (10) and supplying them secondarily, a selector (121) for seiecting either the ordinary instruction buffer (122) or the TAR instruction buffer (123) as an instruction supplying source, and an instruction fetch control unit (102) for fetching, when a TAR filling instruction is executed, one or more instructions specified by the TAR filling instruction, and for controlling the selector (121) to select the TAR instruction buffer (123), in the case where case one or more fetched instructions are repeatedly supplied, thereby to supply an instruction through the selector (121) from the TAR instruction buffer (123).

Description

technical field [0001] The present invention relates to processors and the like that fetch and execute instructions stored in an instruction cache, and more particularly, to a processor capable of executing instructions in a loop portion without accessing the instruction cache. Provide instructions. Background technique [0002] In recent years, digital home appliances such as mobile phones, digital video cameras, and digital video recorders have become more and more popular. And, for processors mounted in these products, processors with low power consumption and high processing capability are required. [0003] In this regard, for example, a processor has been proposed that achieves low power consumption and high processing capability by shortening penalty cycles due to branch prediction errors (see, for example, Non-Patent Document 1). [0004] Specifically, generally, the processor includes two instruction buffers in the part that manages instruction fetching, and any o...

AI Technical Summary

Problems solved by technology

As a result, control when switching instruction buffers becomes complicated

In addition, since the branch destination instruction is fetched from the instruction cache and stored in the second instruction buffer during the decoding stage of the branch instruction, the time available for fetching becomes shorter, making it difficult to sufficiently store and provide the instruction.

As a result, there is a problem that even if the capacity of the instruction buffer is increased to reduce the frequency of accessing the instruction cache memory in order to execute loop processing at a high speed with low power consumption, there is no significant effect. Good results

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