Layout architecture with high-performance and high-density design

A layout and electrical connection technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems of excessively long connecting lines, waste of layout area, and increased difficulty of winding, and achieve enhanced driving capabilities and high-performance design Effect

Inactive Publication Date: 2011-01-12
FARADAY TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the biggest disadvantage of this layout structure is that it is different from the entire area of ​​the P-type MOS region 322. The areas of the N-type MOS regions 321 and 323 are separated. This separation makes some circuits unable to be shared and requires repeated design, which increases the complexity. And it is easy to cause part of the layout area to be wasted
And the connecting wire is too long, which increases the difficulty of winding

Method used

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  • Layout architecture with high-performance and high-density design
  • Layout architecture with high-performance and high-density design
  • Layout architecture with high-performance and high-density design

Examples

Experimental program
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Embodiment Construction

[0034] Figure 4 It is a layout diagram of a high-performance and high-density layout architecture 400 according to an embodiment of the present invention. The standard unit 400 includes a base (not shown), and conductors 401 , 404 , 406 , 408 and device regions 402 , 403 , 405 , 407 are disposed on the base. The conductors 401, 406 have a voltage VCC, and the conductors 404, 408 have a voltage GND.

[0035] The device area 402 is configured with a plurality of P-type metal oxide semiconductor (MOS) transistors for short. The device area 402 is connected to the conductor 401 to obtain the voltage VCC, and the device area 402 is connected to the device area 403 . The element region 403 is configured with a plurality of N-type MOS transistors, the element region 403 is connected to the element region 402 and the element region 405 , and the element region 403 is located under the conductor 404 . The device area 403 can obtain the voltage GND through the connection conductor 40...

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Abstract

The invention relates to an arrangement frame of high property and high density and used for an integrated circuit of standard units. The arrangement frame comprises a substrate, a first conductor, a second conductor, a third conductor, a forth conductor, a first element area, a second element area, a third element area, and a forth element area. The first element area is positioned on the substrate and is close to the first conductor. The second element area is positioned on the substrate and below the second conductor and is close to the first element area. The third element area is positioned on the substrate and below the third conductor and is close to the second element area. The forth element area is positioned on the substrate and between the third element area and the forth conductor.

Description

technical field [0001] The present invention relates to a layout architecture, and more particularly to a layout architecture with high performance and high density design. Background technique [0002] figure 1 It is a layout diagram of an existing standard cell. The existing standard cells C1-C4 are located between the conductors T1 and T2, and can perform different functions such as amplifiers, adders, multipliers, and inverters, respectively. Therefore, the standard cells C1 to C4 are arranged with different widths W1 to W4 according to the complexity of the functions. exist figure 1 Among them, the width W4 is greater than the width W2, so, under the same height H1, the layout area of ​​the standard cell C4 is larger than that of the standard cell C2. Therefore, the standard cell C4 is suitable as a layout structure for a circuit with a relatively complex design or a circuit with a large driving current, and the standard cell C2 is suitable for a layout structure fo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02H01L23/522
Inventor 蔡裕文吴政晃
Owner FARADAY TECH CORP
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