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Concurrent hardware selftest for central storage

A computer system and storage system technology, applied in the field of computer system design, can solve the problems of data clearing or disturbance, achieve the effect of flexible and efficient design, and improve system performance

Inactive Publication Date: 2007-12-05
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

or the data in the just-deallocated memory can be cleared or scrambled

Method used

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  • Concurrent hardware selftest for central storage
  • Concurrent hardware selftest for central storage
  • Concurrent hardware selftest for central storage

Examples

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Embodiment Construction

[0019] The present invention is implemented using parallel self-test hardware provided with a system that contains two main pieces of hardware: a self-test engine and priority logic. When parallel self-test is required, the hardware self-test engine is first set up by firmware. The start and end addresses, address mode, and data mode are initialized. After being set up according to the firmware, the self-test engine will start sending fetch and store commands to the priority logic in the background. Priority logic will take commands from the self-test engine and normal mainline transfers, prioritize them, and send them sequentially to the Processor Memory Array (PMA) portion of the memory subsystem.

[0020] Referring now to the drawings in more detail, it can be seen that Figure 1 is a system block diagram showing how memory transfers are handled.

[0021] In the z9-109 implementation, the MSC (Main Storage Controller) chip has an X port and a Y port, each independently con...

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PUM

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Abstract

Disclosed are a concurrent selftest engine and its applications to verify, initialize and scramble the system memory concurrently along with mainline operations. In prior art, memory reconfiguration and initialization can only be done by firmware with a full system shutdown and reboot. The disclosed hardware, working along with firmware, allows us to do comprehensive memory test operations on the extended customer memory area while the customer mainline memory accesses arc running in parallel. The hardware consists of concurrent selftest engines and priority logic. Great flexibility is achieved by the new design because customer-usable memory area can be dynamically allocated, verified and initialized. The system performance is improved by the fact that the selftest is hardware-driven whereas in prior art, the firmware drove the selftest. More comprehensive test patterns can be used to improve system memory RAS as well.

Description

technical field [0001] This invention relates to computer system design, and more particularly to systems with large central storage. Background technique [0002] One method for testing a memory device having a plurality of memory locations each with a corresponding memory address is known as the memory self-test described by US patent 5033048 issued 1991-07-16. [0003] IBM has provided memory self-test hardware engines to customers for many years. IBM's hardware is usually provided to the customer more than what the customer buys, and the customer usually pays for the configuration of the hardware system according to his needs based on the real-time workload. The hardware system will release reserved resources on demand according to the reconfiguration and initialization that has been done by the firmware at the time of this IML. The storage subsystem resources of the central storage fall into this category, where a customer is allowed to access only the storage he has ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/00G11C29/12G06F11/00
CPCG11C29/52G11C29/44G11C2029/0409G06F11/106
Inventor 乔治·C.·维尔伍德王立勇凯文·W.·卡克
Owner IBM CORP
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