Method of fabricating a tunneling nanotube field effect transistor

Abstract

A method of fabricating a tunneling nanotube field effect transistor includes forming in a nanotube an n-doped region and a p-doped region which are separated by an undoped channel region of the transistor. Electrical contacts are provided for the doped regions and a gate electrode that is formed upon a gate dielectric layer deposited on at least a portion of the channel region of the transistor.

Description

technical field [0001] The present invention generally relates to methods of fabricating devices on semiconductor substrates. More specifically, the present invention relates to methods of fabricating tunneling nanotube field effect transistors on semiconductor substrates. Background technique [0002] Typically, microelectronic devices are fabricated on semiconductor substrates as integrated circuits. Complementary metal-oxide-semiconductor (CMOS) field-effect transistors are one of the core components in integrated circuits. In order to achieve higher performance and packing density of integrated circuits, the size and operating voltage of CMOS transistors are continuously reduced or scaled down. In particular, in such transistors the threshold voltage V th (that is, the voltage required to turn on the transistor) decreases. [0003] The switching characteristics of a CMOS transistor can be described by a parameter known in the art as the inverse sub-threshold slope, w...

AI Technical Summary

Problems solved by technology

Too small a turn-on / turn-off current ratio prevents proper operation of digital circuits including these transistors and is therefore considered to be one of the main challenges in scaling the final device

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