MPU FPGA verification device supporting stochastic instruction testing

Abstract

This invention discloses one artificial valuation FPGA physical prototype validation device through micro processor design, wherein the device comprises the following parts: one main control circuit with one processor interface for connection with validation micro processor; one power and clock generation circuit connected with micro process to be tested; one work memory and one reference memory connected to main control circuit through main control circuit memory interface, wherein the main control circuit has one communication interface with one outer work station.

Description

technical field [0001] The invention relates to microprocessor design verification, in particular to an FPGA (Field Programmable Gates Array, FPGA for short) physical prototype verification device in the simulation verification of general microprocessor design. Background technique [0002] At present, in the functional verification of general-purpose microprocessor design, dynamic simulation is still the dominant verification method. Dynamic simulation verification mainly includes software HDL (Hardware Description Language, HDL for short) simulation and hardware FPGA physical prototype simulation. The advantages of using software HDL simulation method: first, the flexibility of using software simulation is high, and simulation verification can be carried out at various levels of design module level, microarchitecture level and system level; second, the use of software simulation The method can provide a very good debugging environment. Usually, a graphical interface can b...

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Problems solved by technology

However, such a detection mechanism does not provide support in existing FPGA systems.

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