Digital tracking method of synchronous phase angle

Abstract

This invention relates to simultaneous phase angle digital tracing method in the relative technique field and is characterized by the following: first inputting the simultaneous signals into radio measurement circuit to get the frequency division of outer crystal clock of CI and plug parameters of CR; then using the CI, CR as frequency division values input to the plug and division circuit.

Description

technical field [0001] The invention relates to a digital tracking method for a synchronous phase angle. The method can perform precise frequency and phase tracking on an input square wave synchronous signal, and produce an accurate 0.01 electrical angle synchronous pulse signal output, belonging to the technical field of phase tracking. Background technique [0002] In the control field of electrical engineering, such as static var generators, active filters, dynamic voltage restorers and other devices, various control processes usually need to accurately track the frequency and phase of the grid voltage. With the development of digital signal processors (hereinafter referred to as DSP) and programmable logic gate arrays (hereinafter referred to as FPGA), full digital control has become an inevitable trend, and the frequency and phase of the grid voltage are accurately digitally tracked and the synchronous phase angle is obtained. A digital output is already necessary. [...

AI Technical Summary

Problems solved by technology

[0004] The implementation of the existing digital phase-locked loop needs to include multiple links such as digital phase detector, digital filter, numerical control oscillator and feedback frequency divider, which is more complicated to realize, and the parameter design of low-pass digital filter and Transfer function analysis is more difficult

In the digital control system that needs to synchronize the grid voltage, if the digital phase-locked loop chip is used, the complexity and cost of the control system design will be increased. If the digital phase-locked loop is implemented in the FPGA, it will need to occupy a large system resource

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