Double channel DSPEED-ADC_D2G high-speed data collecting plate

A high-speed data acquisition and data acquisition technology, applied in signal transmission systems, instruments, electrical signal transmission systems, etc., can solve the problems of single working mode, only one trigger mode, slow external transmission interface rate, etc., and achieve strong signal processing. effect of ability

Inactive Publication Date: 2008-12-31
BEIJING INSTITUTE OF TECHNOLOGYGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These designs all have the problem of a single working method, either only a small amount of data can be cached, or the external transmission interface is very slow, or there is only one, and there is only one trigger method

Method used

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  • Double channel DSPEED-ADC_D2G high-speed data collecting plate
  • Double channel DSPEED-ADC_D2G high-speed data collecting plate

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0012] The present invention will be further described below in conjunction with accompanying drawing and specific embodiment:

[0013] This ultra-high-speed data acquisition board includes two relatively independent data acquisition channels, each channel includes: an ADC chip model TS83102G0, a data shunt (DeMux) chip model TS81102G0, and 4 FIFO chips model IDT72T40118 . See attached figure 1 , attached figure 2 .

[0014] The sampling clock of ADC is 2 GHz sinusoidal signal provided externally through SMA, and the comparator in the board generates a square wave clock, which is provided to two ADCs. The input signals of the two ADCs are input by two SMAs and directly sent to their respective ADC chips. The ADC outputs the 10-bit data and clock after analog-to-digital conversion to the DeMux chip. The DeMux chip splits the input high-speed data stream into 8-way 10-bit low-speed data stream and slow clock input FIFO module.

[0015] Each channel FIFO is composed of two...

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Abstract

The invention discloses a double-channel DSPEED-ADC_D2G high speed data collection board, which mainly comprises seven power source modules, a double-channel data collection and split module, a two-stage cache module, a collection control processing transmission module, a digital signal assisting processing module, a StarFabric transmission module and a outbound physic interface; board type: CPCI 6U standard board type; working platform: industrial control computer platform. The invention is mainly applied for SAR radar echo signal collection, radar signal scout and receiving, frequency storage interference and data collection sites with high demands on software radio equality sampling rate and input band width. Besides, the invention, which resolves the problems about the triggering control of GHZ sampling rate, data storage and transmission, is provided with a plurality of triggering modes, signal processing mode and data transmission mode.

Description

technical field [0001] The invention relates to an ultra-high-speed data acquisition board and its hardware structure. Background technique [0002] The ultra-high-speed data acquisition board is mainly used in SAR signal echo acquisition, radar signal reconnaissance and reception, storage frequency interference, software radio and other occasions that require ultra-wideband and ultra-high-speed signal acquisition. Under the data acquisition rate of GSPS, I and Q channel synchronization, various trigger modes, real-time storage of data, preprocessing and transmission of collected data, and clock network distribution become very difficult to realize. [0003] Most of the existing data acquisition boards have a sampling rate below 250MSPS and a bandwidth of tens of MHz. These acquisition boards cannot cope with the current broadband signals of hundreds of MHz or even GHz. The few acquisition boards that can work in GSPS mostly input the data collected by ADC directly or separ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G08C19/00
Inventor 高梅国谢民冀连营刘国满宋民张琦
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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