Method for producing semiconductor device

Abstract

When etching ONO laminated construction of SONOS parts, the method uses mixed gas of carbon tetrafluoride (CF4) and fluoroform (CHF3) as main etching gas instead of mixed gas of HBr and C2F6, and uses CHF3 as over etching gas instead of mixed gas of CH2F2 / SF6. Using mixed gas of CF4 and CHF3 accomplishes main etching and over etching step for one time so as to simplify etching technique. Based on good etching selectivity and suitable etching speed, the method controls and buffers effect for etching ONO laminated construction by plasma of etching gas. In procedure for etching wafer thin oxidizing layer of grid electrode, the method is capable of controlling etching depth accurately, stopping etching at oxidation surface at low layer of ONO. Moreover, the method eliminates concave phenomena at sidewall and root part of polysilicon gate caused by transversal etching.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for manufacturing a semiconductor SONOS (silicon-oxide-nitirde-oxide-silicon silicon-oxide-nitride silicon-oxide-silicon) device gate structure. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, semiconductor wafers are developing towards higher component density and high integration. SONOS (silicon-oxide-nitirde-oxide-silicon) devices, as a new generation of low-voltage, high-density non-volatile semiconductor flash memory devices, have attracted increasing attention due to their excellent scaling characteristics . The core structure of the SONOS device is an oxide-nitirde-oxide ONO stack structure formed between the polysilicon gate and the surface of the silicon s...

AI Technical Summary

Problems solved by technology

However, for 65nm and even 45nm process nodes, the thickness of the gate oxide layer is only Left and right, it is etched away and the lateral recess at the root of the polysilicon gate will inevitably degrade the device performance, and the depth of the LDD will be difficult to control

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