Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision

Abstract

A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.

Description

[0001]This application is a Div. of Ser. No. 09 / 169,255 filed Oct. 9, 1998, now U.S. Pat. No. 6,343,356, and claims benefit of Provisional Application No. 60 / 092,148 filed Jul. 9, 1998.FIELD OF THE INVENTION[0002]The present invention relates generally to improvements to processing, and more particularly to advantageous techniques for providing a scalable building block register file which in a first application of the register file provides a low cost lower capacity register file, while in a second application, a higher capacity register file with dynamic reconfiguration support for flexible data type operations is provided. The present invention also relates to advantageous techniques for providing a dynamically reconfigurable register file of variable size width for different levels of data precision operations when executing algorithms demanding variable data types of variable precision requirements and for conducting multiple parallel operations on lower precision data in 32 bi...

AI Technical Summary

Benefits of technology

The present invention provides a way to achieve higher performance and flexibility in accessing data by using two single wide register files that provide a single register model with fewer read and write ports than a single register file of double the capacity would require. The architecture designates one register file as containing even register addresses and the other as containing odd register addresses. The invention also allows for dynamic association of additional register sets with any register in the register file to provide extended precision data width to any selected file register. The double width register file provides the same access width for a simpler programming model and allows for single width accesses across the full register address space. These features and advantages provide higher performance and flexibility in accessing data while reducing costs.

Problems solved by technology

This desire is offset by the hardware cost to implement a wider register file or the hardware cost to implement additional read and write ports.

The problem is how to achieve a dynamically configurable register file with extended precision at a reduced hardware cost without affecting general capabilities including performance.

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