Digital hold in a phase-locked loop

Abstract

A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.

Description

BACKGROUND[0001]1. Field of the Invention[0002]This application relates to clock signal generation in high speed systems and more particularly to generation of clock signals when a reference signal used in generating those clock signals is lost.[0003]2. Description of the Related Art[0004]High speed communication systems require high speed clock signals for transmission and reception of information. For example, in optical communication systems, line cards compliant with standards such as Synchronous Optical Network (SONET) or Synchronous Digital Hierarchy (SDH) (the European counterpart to SONET), utilize clock generation circuits to generate high speed clock signals used in data transmission and reception. In a typical clock generation circuit in such SONET (or SDH) compliant systems, a phase-locked loop (PLL) receives a synchronization input reference clock signal and generates one or more high speed clock signals suitable for use in transmitting or receiving data. According to o...

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Problems solved by technology

However, the clock signal generated in holdover mode may still drift to such an extent as to fail to meet the holdover requirements.

For example, certain PLLs may fail to meet holdover requirements because the voltage controlled oscillators utilized in such systems have too much frequency variation over temperature (e.g., 100 ppm / ° C.).

In addition, certain phase-locked loops, for example, phase-locked loops using digital techniques as described in application Ser. No. 09 / 902,541, filed Jul. 10, 2001, entitled “Digitally-Synthesized Loop Filter Circuit Particularly Useful for a Phase-Locked Loop”, fail to meet the initial accuracy required when first entering holdover mode due to truncation error.

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