Dual gate FinFET

Abstract

A circuit has a fin supported by a substrate. A source is formed at a first end of the fin and a drain is formed at a second end of the fin. A pair of independently accessible gates are laterally spaced along the fin between the source and the drain. Each gate is formed around approximately three sides of the fin.

Description

BACKGROUND[0001]Integrated circuit device performance in the sub 100 nm range is often limited by short-channel effects. Such short-channel effects make further scaling difficult if not impossible. These effects are usually manifested as a reduction in transconductance, an increase in output conductance and a shift in the threshold voltage as transistor gate length is reduced.[0002]Another manifestation of short channel effects is an increase in the sub-threshold current. For low power or for high performance applications, tight control on the sub-threshold drain current and threshold voltage is needed. Challenges to the source-drain doping and requirement for scaled ultra shallow junctions which demand adequate doping abruptness with high doping activation, may be a major limiting barrier to technology development beyond the 65 nm range.BRIEF DESCRIPTION OF THE DRAWINGS[0003]FIG. 1A is a circuit diagram of a dual gate FinFET (Fin type Field Effect Transistor) according to an exampl...

AI Technical Summary

Problems solved by technology

Integrated circuit device performance in the sub 100 nm range is often limited by short-channel effects.

Such short-channel effects make further scaling difficult if not impossible.

Challenges to the source-drain doping and requirement for scaled ultra shallow junctions which demand adequate doping abruptness with high doping activation, may be a major limiting barrier to technology development beyond the 65 nm range.

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