Verification complexity reduction via range-preserving input-to-constant conversion

Abstract

A logic verification program, method and system provide an efficient behavior when verifying large logic designs. The logic is partitioned by cut-nodes that dominate two or more RANDOMS and a check is performed for a given cut-node to determine whether any of the dominated RANDOMS can be merged to a constant by performing satisfiability checks with each RANDOM merged to a constant, to determine whether a range of output values for the given cut-node has been reduced by merging the RANDOM. If the range is not reduced, the RANDOM can be added to the set of merge-able RANDOMS along with the corresponding constant value. If the range has been reduced, the opposite constant value is tried for a node and if the range is reduced for both constants, then the cut-node is abandoned for merging that dominated RANDOM and the next dominated RANDOM is tried.

Description

BACKGROUND OF THE INVENTION1. Field of the Invention[0001]The present invention is related to circuit verification techniques that reduce computational and system memory burdens, and more specifically to logic verification programs, methods and systems that search out and remove dependencies on non-dominated, undefined input values in order to enhance circuit simulation, perform netlist reduction and perform other model simplification.2. Description of Related Art[0002]Modern hardware, software, and hardware / software co-design components have become very large and complex, leading to an increasing diversity of functionality. Such large and complex designs are further complicated by multi-dimensional optimization criteria including delay, area, and power optimizations, as well as the inclusion of additional logic to increase testability, reliability, and configurability. The verification of such complex systems has grown to be extremely challenging if not intractable, with verificati...

AI Technical Summary

Problems solved by technology

Modern hardware, software, and hardware / software co-design components have become very large and complex, leading to an increasing diversity of functionality.

Such large and complex designs are further complicated by multi-dimensional optimization criteria including delay, area, and power optimizations, as well as the inclusion of additional logic to increase testability, reliability, and configurability.

The verification of such complex systems has grown to be extremely challenging if not intractable, with verification resource demands typically having eclipsed the cost of all other aspects of the production of such systems, while in addition frequently increasing the risk of missing subtle design flaws during verification.

Design flaws, particularly those that occur in dedicated hardware, can be very expensive to repair if exposed late in the product development cycle, causing product delays which may eliminate or decrease the profitability of a design, while risking damage due to erroneous computations, including risk to human lives.

Verification typically involves exponentially-growing complexity with respect to the size of the design under verification.

Some verification techniques are more seriously hindered by certain design components than others.

The number of gates in a design often imposes a significant impact on the complexity of analysis of the design functionality, since a large number of gates is typical of a more complicated functionality of the design.

Verification techniques that simulate logic to determine a set of reachable states of a design are typically greatly impacted by the number of state-retaining elements present in the design.

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