Three-dimensional semiconductor memory device and method of fabricating the same

Abstract

A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2015-0036839, filed on Mar. 17, 2015, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein.TECHNICAL FIELD[0002]Exemplary embodiments of the inventive concept relate to a semiconductor device and a method of fabricating the same, and in particular, to a three-dimensional (3D) semiconductor memory device and a method of fabricating the same.DISCUSSION OF THE RELATED ART[0003]The degree of integration of a semiconductor device is a factor of the cost of such device. In the case of two-dimensional (2D) or planar semiconductor memory devices, since their integration is determined by the area occupied by a unit memory cell, integration depends on how small the patterns of the semiconductor can be formed. However, the cost of equipment that forms minute patterns is high.[0004]Thr...

AI Technical Summary

Benefits of technology

The patent describes a semiconductor memory device with a vertical insulating structure and a vertical channel portion. The vertical insulating structure includes a bottom region that protrudes towards the vertical channel portion. The bottom region has a curved profile or a vertical side profile that comes into contact with the vertical channel portion. The vertical channel portion includes a first channel pattern and a second channel pattern. The patent also describes a semiconductor memory device with a common source region and a bottom region that includes an outer surface that contacts the vertical insulating structure. The technical effects of the patent include improved performance and reliability of the semiconductor memory device.

Problems solved by technology

The degree of integration of a semiconductor device is a factor of the cost of such device.

However, the cost of equipment that forms minute patterns is high.

However, manufacturing obstacles are encountered in achieving low-cost, mass-production 3D semiconductor memory devices.

The manufacturing obstacles may affect the reliability of such devices.

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