Low voltage swing buffer

Abstract

An apparatus includes a first circuit of a first type that couples an output node to a first power supply node in response to a first value of a control signal. The apparatus includes a second circuit of a second type to couple the output node to the first power supply node in response to a first value of a first signal having a first voltage swing. The apparatus includes a third circuit of the second type to couple the output node to a second power supply node in response to a second value of the first signal. The apparatus includes a control circuit that generates the control signal based on the first signal and an output signal on the output node. The first, second, and third circuits generate an output signal on the output node. The output signal has a second voltage swing less than the first voltage swing.

Description

BACKGROUND[0001]1. Field of the Invention[0002]This invention relates to integrated circuits and more particularly to circuits used in signal distribution of integrated circuits.[0003]2. Description of the Related Art[0004]In general, integrated circuits use a distribution network to deliver a signal to every element of an integrated circuit that needs that signal. Such signal distribution may consume a substantial amount of a total power budget for a system-on-a-chip (SoC) or other integrated circuit. For example, clock distribution consumes approximately 30% to 40% or more of the total power budget for a typical SoC. As integrated circuit technology advances, power supply voltage levels are not decreasing as fast as the increase in the need for computing power, and integrated circuit technology advances are not generating substantial power savings. For mobile applications, power consumption may influence the cost and complexity, as well as the speed and performance, of electrical ...

AI Technical Summary

Benefits of technology

The patent text discusses a problem in integrated circuits where the power consumption of distributing signals can be a significant portion of the overall power budget. This can be a problem because as technology advances, power supply levels have not kept up with the increasing need for computing power. The invention aims to reduce the power consumption of signal distribution networks on integrated circuits. The patent describes various techniques for achieving this reduction, including the use of low-power clock buffers and pull-down circuits. These techniques can help to decrease the power consumption of the integrated circuit and improve its performance.

Problems solved by technology

Such signal distribution may consume a substantial amount of a total power budget for a system-on-a-chip (SoC) or other integrated circuit.

As integrated circuit technology advances, power supply voltage levels are not decreasing as fast as the increase in the need for computing power, and integrated circuit technology advances are not generating substantial power savings.

For mobile applications, power consumption may influence the cost and complexity, as well as the speed and performance, of electrical components.

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