Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware

Abstract

A GPGPU-compatible architecture combines a coarse-grain reconfigurable fabric (CGRF) with a dynamic dataflow execution model to accelerate execution throughput of massively thread-parallel code. The CGRF distributes computation across a fabric of functional units. The compute operations are statically mapped to functional units, and an interconnect is configured to transfer values between functional units.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Patent Application No. 61 / 969,184, filed Mar. 23, 2014, which is herein incorporated by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]This invention relates to administration of task execution in a digital data processing system. More particularly, this invention relates to transaction and job processing between multiple processors, computers, or digital data processing systems[0004]2. Description of the Related Art[0005]The meanings of certain acronyms and abbreviations used herein are given in Table 1.TABLE 1Acronyms and Abbreviations8-NNEight Nearest NeighborsALUArithmetical-Logical UnitCDFGControl Data Flow GraphCGRFCoarse Grain Reconfigurable FabricCUDACompute Unified Device ArchitectureDRAMDynamic Random Access MemoryFCFRFirst Come First ReadFIFOFirst-In-First-OutFLOPFloating Point OperationFPUfloating point unitFR-FCFSFirst Ready - First Come First ...

AI Technical Summary

Benefits of technology

The invention is a design that combines a CGRF and a dynamic dataflow execution model to accelerate the execution of massively thread-parallel code. This design is different from previous known CGRF designs which favor single-threaded performance over multi-threaded throughput. The use of a dynamic dataflow execution model means that the code can be executed across multiple functional units in a fabric, making it energy-efficient and able to deliver good single-threaded performance. The design also allows for distributed control and statical instruction mapping, which negates the need for a centralized register file. The Single Graph Multiple Flows (SGMF) execution model disclosed in the invention combines pipelining and dynamic dataflow to extract thread-level parallelism in CGRFs, which can yield enough thread-level parallelism to hide medium-latency events such as L1 cache misses.

Problems solved by technology

Nevertheless, existing GPGPUs employ a von-Neumann compute engine and, therefore, suffer from the model's power inefficiencies.

These inefficiencies dramatically reduce the energy efficiency of modern GPGPUs (as well as that of general-purpose von-Neumann processors).

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