Stacked wafer structure and fabricating method thereof

Abstract

A stacked wafer structure includes a CIS wafer, an ISP wafer, a lamination layer, a through silicon via and a pixel device. The CIS wafer bonds to the ISP wafer through the lamination layer. The pixel device is disposed on the CIS wafer. The through silicon via penetrates either the CIS wafer or the ISP wafer to connect devices in CIS wafer to the devices in ISP wafer electrically.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to stacked wafer structure and method of fabricating thereof, and more particularly, to a stacked wafer structure having a trough silicon via penetrate either a CIS wafer or a ISP wafer to electrically connect the device in the CIS wafer to the device in the ISP wafer.[0003]2. Description of the Prior Art[0004]General image sensors are roughly classified into charge coupled device (CCD) image sensors and CMOS image sensors (CISs). Compared with the CCD image sensors, the CISs are widely used in portable apparatuses.[0005]A pixel array of a CIS includes a plurality of pixels, and each of the pixels may generate an image signal from an optical signal. In detail, each of the pixels integrates photocharges corresponding to the amount of light incident using a photodiode and generates an analog pixel signal corresponding to the integrated photocharges.[0006]In general, the analog pixel signal ou...

AI Technical Summary

Benefits of technology

This patent proposes methods and structures for assembling two wafers, one with conductive elements and active devices (ISP wafer) and another with a simple dielectric layer and conductive stacks (CIS wafer), at the chip level while reducing their size and improving their characteristics. The two wafers are bonded together using a lamination layer, and through silicon via is used to connect the conductive elements between the wafers. This allows for a more compact and efficient semiconductor device design. The technical effects of this patent include reducing the size and improving the functionality of semiconductor devices.

Problems solved by technology

In a conventional fabricating process, the CIS circuits and ISP circuits are formed on the same substrate, however, results in an increase in the number of processes and high cost.

During the BIS process, the substrate with the ISP circuits has no alternative but to undergo the BIS process, which will increase the fabricating time.

Moreover, the line width of the ISP circuits will be compromised because the CIS circuits and the ISP circuits are fabricated by the same lithographic process, which may cause degradation in the characteristics of the ISP device.

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