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Register renaming of a partially updated data granule

a technology of register renaming and data granule, applied in the field of data processing systems, can solve the problems of short dependency chain, hinder rapid operation and efficient scheduling, and similar problems can also arise with other data granules, so as to prolong the dependency chain, enhance the ability to issue, and prolong the effect of dependencies

Active Publication Date: 2010-12-09
ARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides an apparatus for processing data that includes a processing circuitry, a register store, and a renaming circuitry. The processing circuitry is responsible for performing data processing operations on a stream of program instructions, while the register store stores data values resulting from these operations. The renaming circuitry is responsible for identifying destination registers to store the data values, and the rename table circuitry is responsible for identifying tag values associated with different flags within the data values. The invention also provides a technique for identifying which parts of a data granule are updated by certain program instructions and which parts are not. The invention is well-suited for processing data in parallel and out-of-order execution of program instructions. It is also well-suited for processing data in systems with multiple processing operations and flag values.

Problems solved by technology

A problem with this approach is that the dependency chain is very short with most instructions requiring as a source the flag register as generated by the preceding instruction.
This hinders rapid operation and efficient scheduling.
Similar problems can also arise with other data granules that are dependencies between instructions.

Method used

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  • Register renaming of a partially updated data granule
  • Register renaming of a partially updated data granule
  • Register renaming of a partially updated data granule

Examples

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Embodiment Construction

[0061]FIG. 1 illustrates a processor 2 incorporating an instruction pipeline having a fetch stage 4, a decode stage 6, a rename stage 8, an issue stage 10 and multiple execution stages 12, 14, 16. Such a processor 2 is suited to support of out-of-order program execution as a stream of program instructions are fetched from memory by the fetch stage 4 and then subject to decoding, register renaming and issue by the issue stage 10. The instructions will typically be executed in parallel within the execution stages 12, 14, 16 over multiple processing cycles.

[0062]The processor 2 includes a register store of virtual registers 18. These virtual registers are mapped to architectural registers as specified by the program instructions which are being executed. A rename table 20 stores tag data indicating the relationship between architectural registers and virtual registers at any point in the program flow. The use of register renaming and a rename table will in themselves be familiar to tho...

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Abstract

A processor 2 supporting register renaming has a rename table 20 in which the flag register has multiple tag values associated therewith. These tag values indicate which virtual register corresponds to a destination flag register of the oldest instruction which wrote a still up-to-date value of a subset of the flags.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]This invention relates to the field of data processing systems. More particularly, this invention relates to register renaming within data processing systems.[0003]2. Description of the Prior Art[0004]It is known to provide out-of-order data processing systems which utilise register renaming techniques to remove or reduce data dependencies between instructions in a manner which permits a higher degree of parallelisation and / or out-of-order instruction issue. Within such systems, as an instruction is decoded it is determined which architectural registers will serve as destination registers for that instruction and which architectural registers will serve as source registers for that instruction. The system is provided with virtual registers that are greater in number than the architectural registers and may be mapped to architectural registers via a rename table. The rename table will indicate which virtual registers are...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F9/30
CPCG06F9/30094G06F9/384G06F9/3838G06F9/30105
Inventor HARDAGE, JAMES NOLAN
Owner ARM LTD
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