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Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS

a technology of silicon transistors and threshold voltages, which is applied in the field of semiconductor structure, can solve problems such as non-ideal thresholds, and achieve the effect of promoting the necessary flatband voltage shift and altering the effective alignment of the workfunction of the material stack

Inactive Publication Date: 2008-10-23
AURIGA INNOVATIONS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The rare earth metal layer shifts the flatband voltage to appropriate values, achieving the desired threshold voltage of about 0.1 V for n-channel MOSFETs while maintaining high electron channel mobilities, thereby stabilizing the voltage profiles.

Problems solved by technology

It is emphasized that prior art Si MOSFETs fabricated with hafnium oxide as the gate dielectric suffers from a non-ideal threshold voltage when n-MOSFETs are fabricated.

Method used

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  • Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS
  • Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS
  • Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS

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example

[0059]In this example, an nMOSCAP was prepared utilizing a material stack of the present invention and it was compared with a prior art nMOSCAP which did not include the inventive material stack. Specifically, a material stack comprising SiO2 / HfO2 / 0.8 nm La2O3 / 30 nm TiN / PolySi stack (Inventive) was prepared utilizing the processing steps mentioned above and that material stack was used as a component of an nMOSCAP. A prior art material stack, not including La oxide was prepared and was used a component for a prior art nMOSCAP (Prior Art). Each material stack after processing on a Si substrate was subjected to a 1000° C. rapid thermal anneal in nitrogen, followed by a 500° C. forming gas anneal.

[0060]FIG. 3 shows the CV curves of the two nMOSCAP. The CET (Capacitance Equivalent Thickness) and the EOT (Equivalent Oxide Thickness) of the Inventive material stack were 10.2 Å and 6.5 Å, respectively. The CET and the EOT of the Prior Art material stack were 14.7 Å and 10.5 Å, respectively...

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Abstract

The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising:a hafnium-based dielectric; a rare earth metal-containing layer located atop of, or within, said hafnium-based dielectric; an electrically conductive capping layer located above said hafnium-based dielectric; and a Si-containing conductor.

Description

RELATED APPLICATION[0001]This application is a continuation application of U.S. Ser. No. 11 / 118,521, filed Apr. 29, 2005.FIELD OF THE INVENTION[0002]The present invention generally relates to a semiconductor structure, and more particularly to a material stack useful in metal oxide semiconductor capacitors (MOSCAPs) and metal oxide semiconductor field effect transistors (MOSFETs) that includes a rare earth metal (or rare earth-like)-containing layer present on top of, or within, a dielectric layer which is capable of stabilizing the threshold voltage and flatband voltage of a Si-containing conductor. Specifically, the presence of the rare earth metal (or rare earth-like)-containing layer induces a band bending in a semiconductor substrate so as to shift the threshold voltage to more negative values than when such a layer is not used.BACKGROUND OF THE INVENTION[0003]In standard silicon complementary metal oxide semiconductor (CMOS) technology, n-type field effect transistors (pFET) u...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L29/76
CPCH01L21/28167H01L21/28185H01L21/28194H01L29/4966H01L29/517
Inventor BOJARCZUK, NESTOR A.CHUDZIK, MICHAEL P.COPEL, MATTHEW W.GUHA, SUPRATIKJAMMY, RAJARAONARAYANAN, VIJAYPARUCHURI, VAMSI K.
Owner AURIGA INNOVATIONS INC
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