Systems and apparatus with programmable memory control for heterogeneous main memory

Abstract

A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This patent application claims the benefit of U.S. Provisional Patent Application No. 60 / 956,681 entitled PROGRAMMABLE MEMORY CONTROL FOR HETEROGENEOUS MAIN MEMORY filed on Aug. 17, 2007 by Kenneth Alan Okin et al.; and further claims the benefit of U.S. Provisional Patent Application No. 60 / 827,421 entitled SUBSTITUTION OF A PROCESSOR WITH A BUILT IN DRAM MEMORY CONTROLLER BY A NON-DRAM MEMORY CONTROLLER TO CONTROL ACCESS TO NON-DRAM TYPE MEMORY MODULES filed on Sep. 28, 2006 by inventors Kumar Ganapathy et al.; and U.S. Provisional Patent Application No. 60 / 862,597 entitled EXPANSION OF MAIN MEMORY IN A MULTPROCESSOR SYSTEM WITH A NON-DRAM MEMORY CONTROLLER TO CONTROL ACCESS TO NON-DRAM TYPE MEMORY filed on Oct. 23, 2006 by inventors Kumar Ganapathy et al.FIELD [0002] This application generally relates to memory controllers for controlling access to memory modules in main memory. BACKGROUND [0003] A computing system may have a homogen...

AI Technical Summary

Problems solved by technology

Due to data skew and other timing considerations, typical main memory designs limit the number of DIMMS in a memory channel to a small number.

A memory erase operation in non-volatile memory integrated circuits also takes more time than a read access.

These longer delays make the program and erase accesses to the non-volatile memory module non-deterministic events.

That is, one may not know beforehand how long it will take a write operation or an erase operation to be completed by a non-volatile memory module.

The memory channel bus may be limited as to the number of integrated circuits that may directly couple thereto, due to loading and timing considerations.

Limiting the number of ranks of memory to a predetermined number can limit the data bandwidth of the memory module and the memory channel.

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