Inter-sequence permutation turbo code system and operation methods thereof

Abstract

A high performance real-time turbo code system is proposed. The proposed system exploits cooperative coding architecture and a proper decoding scheduling to achieve low error rate within a constrained latency. Permutation schemes and hardware embodiments utilizing the cooperative coding are also shown. Various memory saving techniques are provided to reduce memory usage in both encoder and decoder. The proposed system is compatible with 3rd generation mobile standards and cost of designing new parts exclusively for the proposed system can be minimized. This invention can provide substantial coding and system capacity gains for real-time applications in a wireless environment.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a turbo code system, more specifically, a turbo code system utilizing cooperative coding architecture and a proper decoding scheduling to achieve high performance real-time encoding and decoding. [0003] 2. Description of Related Art [0004] Turbo Code (TC) was invented in 1993, which renders extraordinary, near Shannon limit performance by applying the iterative decoding algorithm. Following researches on the area of Forward Error-Control (FEC) were inspired from this primitive code structure and decoding algorithm. We shall thus refer to any FEC system that utilizes the so-called “Turbo Principle” in decoding as a Turbo Code System (TCS). [0005] Codeword length influences the performance of TCS. TCS with long codeword length performs excellently but decoder of the TCS has large decoding latency and hardware complexity. Moreover, the decoder requires considerable number of iterations ...

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Benefits of technology

[0007] Cooperative decoding can improve performance of TCS with short codeword length. Besides, conventional A Posteriori Probability (APP) decoding modules and interleaving techniques can be applied and the feature of “Backward Compatible” is attainable. More than one schedulers can be applied for scheduling of cycles of APP decoding (or called APP decoding runs) or memory releasing.

[0010] Memory usage would be the most critical implementation problem for the cooperative TCS. Decoding more than ten sequences at the same time requires large memory space for the temporary received samples. Moreover, an ISP between sequences also requires buffers storing probability measure for the nearby sequences. In the present invention, a termination test is used to halt decoding. In cooperative TCS, the termination test can be further used for providing more reliable probability measure and releasing memory. In summary, the termination test reduces power consumption and decoding latency, assists in the decoding of the other sequences, and makes the utilization of memory economic.

Problems solved by technology

Memory usage would be the most critical implementation problem for the cooperative TCS.

Decoding more than ten sequences at the same time requires large memory space for the temporary received samples.

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