Interposers with alignment fences and semiconductor device assemblies including the interposers

Abstract

An interposer includes a fence that orients or aligns a semiconductor device, such as a flip-chip type semiconductor device, with an interposer substrate. The fence may include edges that are configured to progressively align a semiconductor device with the interposer substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the interposer substrate. The fence may comprise a unitary structure or a plurality of mutually adhered regions.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of application Ser. No. 10 / 648,163, filed Aug. 26, 2003, pending, which application is a continuation of application Ser. No. 09 / 843,119, filed Apr. 26, 2001, now U.S. Pat. No. 6,634,100, issued Oct. 21, 2003, which is a divisional of application Ser. No. 09 / 533,407, filed Mar. 23, 2000, now U.S. Pat. No. 6,529,027, issued Mar. 4, 2003.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates generally to an interposer configured to receive a semiconductor device for testing. More specifically, the invention pertains to such a test interposer having an alignment fence for receiving and aligning semiconductor devices, such as flip-chip type semiconductor dice, ball grid array (BGA) packages, and chip scale packages (CSPs), with test sockets of the interposer. The present invention also relates to methods for fabricating such a test interposer. [0004] 2. Background...

AI Technical Summary

Benefits of technology

"The present invention provides an interposer for aligning and connecting a semiconductor device to a test substrate. The interposer includes a semiconductor substrate with contact pads on the top side and conductive structures protruding from the bottom side. The interposer also has a fence with raised periphery and recessed regions to align the semiconductor device and establish electrical connection. The fence can be fabricated using computer-controlled, 3-D CAD initiated, stereolithographic techniques. The technical effects of the invention include improved alignment accuracy and more reliable electrical connection between the semiconductor device and the test substrate."

Problems solved by technology

However, it is now recognized that conventional packaging processes may cause significant numbers of semiconductor devices to fail.

For example, as a semiconductor device is being encapsulated, the protective material may cause particulate die coat penetration, “bond wire sweep,” which may break electrical connections made by the bond wires or cause electrical shorts between adjacent bond wires, and other problems.

Some state of the art semiconductor devices lack conventional packages (e.g., leads and encapsulants) or are minimally packaged.

When these types of semiconductor devices are tested, the solder bumps or other conductive structures protruding therefrom may not properly align with the corresponding test sockets of a test substrate so as to establish adequate electrical contacts between the tested semiconductor device and the test substrate.

Moreover, if misalignment occurs, the conductive structures may be damaged.

Nonetheless, the conductive structures protruding from a semiconductor device to be tested may be damaged when assembled with such an interposer.

Moreover, since the recesses of such interposers are configured to receive the conductive structures of a semiconductor device without stressing, deforming, or otherwise damaging the conductive structures, the interposer may fail to make adequate electrical connections between some of the conductive structures and their corresponding test pads or sockets of the test substrate.

Moreover, test interposers typically lack any alignment component other than the recesses thereof.

Accordingly, it appears that the art is lacking a structure for aligning the conductive structures of a semiconductor device with corresponding test pads or sockets of a test substrate without stressing or damaging the conductive structures while facilitating adequate electrical connections between the conductive structures and the test pads or sockets.

However, to the inventors' knowledge, stereolithography has yet to be applied to mass production of articles in volumes of thousands or millions, or employed to produce, augment or enhance products including other pre-existing components in large quantities, where minute component sizes are involved, and where extremely high resolution and a high degree of reproducibility of results are required.

Furthermore, conventional stereolithography apparatus and methods fail to address the difficulties of precisely locating and orienting a number of pre-existing components for stereolithographic application of material thereto without the use of mechanical alignment techniques or to otherwise assure precise, repeatable placement of components.

In particular, stereolithography has not been employed to fabricate interposers for aligning and connecting a semiconductor device to a test substrate.

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