Methods for preventing fixed pattern programming

Abstract

A method for preventing fixed pattern programming, the method including programming data into a pattern of memory cells in a memory array, and preventing fixed pattern programming by periodically scrambling the data so that the data is stored in a different pattern of memory cells in the memory array.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] The present application claims priority from U.S. Provisional Application Ser. No. 60 / 644,569, filed Jan. 19, 2005, which is incorporated herein by referenceFIELD OF THE INVENTION [0002] The present invention relates generally to operating memory cells of non-volatile memory (NVM) arrays, such as programming and erasing, and particularly to methods for preventing large differences in the program and erase history of cells, such as by data scrambling. BACKGROUND OF THE INVENTION [0003] Modern day non-volatile memory products incorporate the ability to electrically program and erase the memory cells. In most cases, the erase operation is performed on a subset of cells and not individually cell-by-cell, as normally performed during the programming operation. This means that erasure conditions are applied to the subset until the last (slowest) cell finishes erasure, including verification that the cell has passed a predetermined level (eras...

AI Technical Summary

Benefits of technology

[0014] The present invention seeks to provide methods for preventing fixed pattern programming, which may prevent large differences in the program and erase history of cells of memory arrays, as is described hereinbelow. The invention is described in detail hereinbelow with reference to memory cells of NVM arrays, and particularly to single bit, dual bit, multi-bit and multi-level NROM cells. However, it should be emphasized that the invention is not limited to NROM arrays.

[0015] There is thus provided in accordance with an embodiment of the invention a method for preventing fixed pattern programming, the method including programming data into a pattern of memory cells in a memory array, and preventing fixed pattern programming by periodically scrambling the data so that the data is stored in a different pattern of memory cells in the memory array.

Problems solved by technology

For tunneling enhanced hot hole injection, the process shown in FIG. 2 usually has to be performed on both sides of the memory cell separately, resulting in longer erase time and lower performance

Over-erased cells may become leaky, i.e., conduct current without being biased to the “on” state (positive gate voltage for an n-MOSFET based memory cell) Over-erased cells may become hard to program, i.e., require excessive voltages and time to bring them to the programmed state (above a predefined level, program verify level) A substantial difference in the operating conditions (program and erase) may develop between cells which have been over-erased and cells which have not been over-erased.

The sum of these effects may result in failure of the memory device, i.e., loss of data integrity.

A programming tail is shown to have formed, due to the lack of sufficient over-erasure prevention measures

However, disadvantages include additional overhead (reduced performance) and design complexity.

However, this carries a substantial performance penalty in time and power.

However, this method also carries a substantial performance penalty in time and power.

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