Method of manufacturing semiconductor device having notched gate MOSFET

Abstract

Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed .on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area.

Description

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS [0001] This application claims the benefit of Korean Patent Application Nos. 10-2005-0002877 filed on 12 Jan. 2005 and 10-2005-0015372, filed on Feb. 24, 2005, in the Korean Intellectual-Property Office, the contents of which are incorporated herein in their entirety by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device, by which process integration of a transistor capable of a multi-bit operation on a cell array area and a metal oxide semiconductor field effect transistor (MOSFET) on a peripheral circuit area is facilitated simultaneously. [0004] 2. Description of the Related Art [0005] Silicon-oxide-nitride-oxide-silicon (SONOS) or metal-oxide-nitride-oxide-silicon (MONOS) devices have been proposed as non-volatile memory devices that are widely used i...

AI Technical Summary

Benefits of technology

[0007] The present invention provides a method of manufacturing a semiconductor device, by which problems caused upon formation of a transistor having a reduced size required by a scaling technique for obtaining a super-highly integrated device can be solved, and a process of forming a cell transistor capable of a multi-bit operation and a process of forming a perimeter circuit transistor can be easily integrated with each other.

[0032] According to the present invention, a process of integrating a memory cell of a non-volatile memory device into a peripheral circuit is simplified, and a transistor for a peripheral circuit area manufactured simultaneously with a cell transistor may have a notch gate structure to thus reduce leakage current in a gate. Additionally, an overlap capacitance between a source / drain and the gate is reduced, and the performance of the memory device is improved.

Problems solved by technology

Hence, integrating the stacked SONOS transistor together with a logic product having a low initial threshold voltage Vth into a single chip is difficult due to the high initial threshold voltage Vth.

Also, in a stacked SONOS-type cell transistor, electrons trapped in a storage node layer within an ONO structure may move horizontally along the storage node layer, and thus an erasing operation may not be properly performed.

Furthermore, as an FET is scaled to a high level with rapid development of the semiconductor industry, various problems, such as an increase in leakage current due to a reduction of the size of a semiconductor device, occur.

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