High speed low power 4-2 compressor

Abstract

A high speed low powered 4-2 compressor according to the present invention performs an XOR / XNOR operation of input data by using a single input type NAND / NOR logic circuit and a dual input type NAND / NOR logic circuit. Thus, delays to generate complementary signals are avoided. In addition, the 4-2 compressor uses a single railed multiplexer instead of a dual railed multiplexer, so that gate drive nodes and internal load capacitance are reduced. As a result, circuit area and power consumption of the 4-2 compressor are reduced.

Description

[0001] This application is a continuation-in-part application of U.S. application Ser. No. 10 / 023,686 filed on Dec. 18, 2001, the contents of which are herein incorporated by reference in their entirety.FIELD OF THE INVENTION [0002] The present invention generally relates to a logic circuit and, more particularly, to a 4-2 compressor for a multiplier. BACKGROUND OF THE INVENTION [0003] Multiplication is one of the primary operations in general-purpose microprocessors and special purpose digital signal processors. The speed of the multiplication operation often directly determines how fast the processors are capable of operating. Generally, a multiplier generates plural partial summation results and then sums the partial results to compute a product. The summation performance influences the performance of the multiplier. However, as technology progresses, a user demands increasingly fast data processing systems. To satisfy the demand, the multiplier circuit grows in complexity, and, ...

AI Technical Summary

Benefits of technology

[0013] It is therefore an object of the present invention to provide a high-speed low-power 4-2 compressor by reducing the total internal load capacitance and reducing the circuit area and power consumption of the 4-2 compressor.

[0022] The first inverter may comprise a P type transistor and a N type transistor having a current path between a power supply voltage source and an output port of the NOR gate in series, and a control electrode controlled by the first input data “a”. The first full-swing means may comprise a P type transistor having a current path between an output port of the first inverter and the output port of the NOR gate, and control electrode controlled by the first input data “a”. The first full-swing means may be turned on when the output signal of the NOR gate is the second logic level, and increases the voltage level of the output signal of the first inverter as high as the power supply voltage level.

[0023] The second inverter may comprise a P type transistor and a N type transistor having a current path between a ground voltage source and an output port of the NAND gate in series, and a control electrode controlled by the output of the NOR gate. The second full-swing means may comprise a N type transistor having a current path between an output port of the second inverter and the output port of the NAND gate, and control electrode controlled by the first input data “a”. The second full-swing means is preferably turned on when the output signal of the NAND gate is the first logic level, and decreases the voltage level of the output signal of the second inverter as low as the ground voltage level.

Problems solved by technology

However, as technology progresses, a user demands increasingly fast data processing systems.

To satisfy the demand, the multiplier circuit grows in complexity, and, as a result, the multiplier occupies an increasingly larger area of a central processing unit (CPU) to be embedded in the data processing system.

Thus, a significant amount of circuit area is required to implement a multiplier for input data of large bit width.

Images