Method and device for managing transmitting buffer area in field programmable gate array

Abstract

The present invention relates to method and device for managing the transmission buffer area in FPGA. Inside the FPGA, there are defined buffer area memory unit, write-in control unit, write/read pointer register, total length/written length register, state indication unit and read out unit. The data frames to be transmitted is first read out from the plugged RAM in several times with the write-in control unit, then written to the buffer area memory unit in FPGA, and finally read out from the buffer area memory unit and sent out with the read out unit. The present invention has very small FPGA block RAM resource occupied by the buffer area even if in case of long data frame.

Description

technical field [0001] The invention relates to a field programmable gate array (FPGA), in particular to a method and a device for managing a sending buffer in the field programmable gate array (FPGA). Background technique [0002] In the current FPGA design in the communication field, it is often necessary to temporarily store the processed data frame in the external large-capacity RAM, and then move the data frame into the sending buffer inside the FPGA, and finally send it out. Usually the method is that the capacity of the sending buffer is at least one full data frame length. Whenever there is data to send and the space in the first-in-first-out buffer (FIFO) exceeds the frame length; start moving the entire packet into the FIFO. The advantage of this method is that the processing method is simple. However, when the maximum length of the processing frame type is relatively long and the number of transmission channels is relatively large, the required FPGA internal sto...

AI Technical Summary

Problems solved by technology

However, this patent cannot solve the problem that the buffer occupies a large number of memory block (BLOCKRAM) resources inside the FPGA when the length of the frame to be processed is very long

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