Test method for testing data memory

Abstract

Test method for testing a data store having an integrated test data compression circuit (16), where the data store (1) has a memory cell array (10) with a multiplicity of addressable memory cells, read / write amplifiers (12) for reading and writing data to the memory cell via an internal data bus (12) in the data store (1), and a test data compression circuit (16) which compresses test data sequences, which are each read serially from the memory cell array (10), with stored reference test data sequences in order to produce a respective indicator data item which indicates whether at least one data error has occurred in the test data sequence which has been read.

Description

technical field [0001] The present invention relates to a test method for testing data memories and a data memory with an integrated test data compression circuit for cheaply testing fast semiconductor memories, in particular DRAMs operating at very high operating clock frequencies ( Dynamic Random Access Memory) memory, and SRAM (Static Random Access Memory) memory. Background technique [0002] figure 1 A test structure according to the prior art is shown. A circuit to be tested DUT (device under test) is connected to an external test unit through a control bus, a data bus and an address bus. The external test unit uses the test data generator to generate test data, and the test data is applied to the memory DUT to be tested through the data bus line in the data bus. The address bus is used to address the memory cells to be tested in the memory to be tested. In this case, test data is written to the addressed memory cell via the data bus, and then read again. The exte...

AI Technical Summary

Problems solved by technology

Therefore, at very high data transfer rates for testing data memories, a test unit with relatively complex circuitry and thus increased cost is required

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