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Flip-flop circuit

A technology of triggers and circuits, applied in electrical components, generating electrical pulses, pulses, etc., to prevent unnecessary changes, reduce power consumption, and reduce the number of

Inactive Publication Date: 2004-05-19
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this way, in Figure 13 of prior art circuits that contain circuits that dissipate power as

Method used

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Examples

Experimental program
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Effect test

no. 1 Embodiment

[0054] figure 1 A circuit diagram showing a flip-flop circuit in the first embodiment of the present invention. In the figure, D denotes an input terminal, CK denotes a clock terminal, and Q denotes an output terminal. 1 denotes a dynamic type input part, 2 denotes a latch circuit, 3 denotes a control part, and 4 denotes a static type output part.

[0055]The control unit 3 has a first node n1, and controls the operation of the input unit 1 using a signal of the first node n1 as a control signal. The input unit 1 receives a clock signal from the clock terminal CK (hereinafter simply referred to as the clock signal CK) and an input signal from the input terminal D (hereinafter referred to as the input signal D), and has a second node n2 from which n2 output signal. The latch circuit 2 receives an output signal from the second node n2 of the input unit 1, has a third node n3, latches the output signal from the input unit 1, and outputs a latch signal from the third node n3. ...

no. 2 Embodiment

[0074] Refer to the following image 3 A flip-flop circuit according to a second embodiment of the present invention will be described. In addition, in the following embodiments, components having the same functions as those in the first embodiment described above are denoted by the same reference numerals, and description thereof will be omitted.

[0075] image 3 The flip-flop circuit shown and described in the first embodiment above figure 1 The circuits of 1 and 2 have substantially the same configuration, and the difference is that a delay circuit 10 is added to the control unit 3 . which is, image 3 In order to delay the control signal applied from the first node n1 to the gate of the NMOS transistor MN3 of the input unit 1, the control signal at the first node n1 is delayed by two inverter circuits INV5 and INV6 connected in series. The circuit 10 is then applied to the gate of the NMOS transistor MN3 of the input section 1 . Here, the connection point between th...

no. 3 Embodiment

[0080] A flip-flop circuit according to a third embodiment of the present invention will be described below with reference to the drawings.

[0081] Figure 4 A circuit diagram showing a flip-flop circuit of this embodiment. basic composition and image 3 The flip-flop circuit shown is the same. In this example Figure 4 circuit, just put the image 3 The arrangement position of the PMOS transistor MP3 in the second embodiment shown is changed. That is, in image 3 The middle gate is connected to the fourth node n4 and is connected to the PMOS transistor MP3 between the power supply and the first node n1. In this embodiment, the gate is connected to the second node n2 of the input part 1 and is connected in parallel with the NMOS transistor MN4. connection for pulling up the first node n1 to the power supply potential.

[0082] In this example Figure 4 of the flip-flop circuit, the hold image 3 In the case of the function of the flip-flop circuit in , when the input...

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Abstract

In a flip-flop circuit which includes an input section using a dynamic circuit and an output section using a static circuit and which captures data during a period of a pulse width shorter than a clock cycle, the number of transistors, circuit area and power consumption are reduced. In FIG. 1, an output signal of an inverter circuit (INV1) constituting a latch circuit (2) connected to the output terminal of an input section (1) is used as an input signal of a control section (3). Thus, a control signal output from the control section (3) to the input section (1) is stabilized, thereby suppressing unnecessary operation of circuit elements and reducing unnecessary power consumption. In addition, the configuration of the control section (3) is simplified. As a result, the number of transistors constituting the circuit and the circuit area can be reduced.

Description

technical field [0001] The invention relates to a flip-flop circuit with high-speed action, in particular to a flip-flop circuit with few transistors and low power consumption. Background technique [0002] In general, among logic circuits in semiconductor integrated circuits, flip-flop circuits have a large influence on area, power consumption, and critical path delay, and it is desired to reduce the area, power consumption, and speed of flip-flop circuits. [0003] Conventionally, for high-speed applications, there is a flip-flop circuit using a latch circuit that performs data access during a pulse width period shorter than a clock cycle. Hereinafter, a prior art example of a flip-flop circuit having such a configuration will be described. [0004] Figure 13 A configuration example of a flip-flop circuit called SDFF (Semi-Dynamic Flip-Flop) is shown. [0005] exist Figure 13 Among them, D represents an input terminal, CK represents a clock terminal, and Q represents a...

Claims

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Application Information

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IPC IPC(8): H03K3/012H03K3/037
CPCH03K3/012H03K3/037
Inventor 平田昭夫袛园雅弘中西和幸
Owner PANASONIC CORP
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